{"id":462462,"url":"https://alion.io/job/astera-labs-tech-lead-formal-verification","title":"Tech Lead, Formal Verification","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":87,"open_postings":53,"ghost_share":0,"stale_share":0.302,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Leadership","role_family":"Leadership","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":38000,"max_usd":102000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":27},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Cadence JasperGold","optional":true},{"name":"Synopsys VC Formal","optional":true}],"status":"live","first_seen_at":"2026-08-03T18:23:59Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-17T06:30:59Z","board_verified":true,"closed_at":null,"days_open":74,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":74},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nWe are looking for a Tech Lead, Formal Verification Engineer with 5-10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs' next-generation connectivity and AI infrastructure products.\nKey Responsibilities \nDevelop comprehensive formal verification plans from architecture and design specifications by identifying critical design properties, protocol requirements, and micro-architectural invariants.\nDevelop and execute formal verification environments, assertions, properties, and checkers.\nDrive proof convergence through advanced abstraction and complexity reduction techniques.\nCollaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.\nEvaluate, deploy, and scale formal verification methodologies, flows, and tools across projects.\nImprove verification productivity through reusable methodologies, automation, and best practices.\nEnsure comprehensive design correctness and provide technical leadership and mentorship across multiple projects.\nDrive bug triage, root-cause analysis, and resolution in collaboration with cross-functional teams.\nSupport project planning by estimating verification effort, tracking execution progress, identifying risks, and driving mitigation plans.\nParticipate in design reviews and contribute to verification sign-off strategies and quality metrics.\nPromote assertion-driven design practices and formal verification adoption across engineering teams.\nRequired Qualifications \nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. \n5-10 experience in semiconductor verification, including significant formal verification experience.\nExpert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques. \nHands-on experience with one or more formal verification tools - JG, VCF preferably. \nExperience verifying complex protocols, control logic, and SoC or subsystem-level designs. \nStrong scripting skills in Python, Perl, Tcl, or Shell.\nExcellent analytical, debugging, and problem-solving capabilities\nExperience leading technical efforts or mentoring team members. \nStrong communication and cross-functional collaboration skills. \nPreferred Qualifications\nExperience with industry-standard formal verification tools such as JasperGold, VC Formal, or equivalent solutions.\nExperience verifying high-speed protocols and interfaces including PCIe®, UALink™, CXL®, Ethernet, SerDes, or related technologies.\nKnowledge of NoC architectures, cache coherency protocols, memory subsystems, and interconnect fabrics.\nExperience with formal bug hunting, proof-based verification, and coverage-driven verification methodologies.\nPrior experience leading technical teams and mentoring engineers.\nExposure to simulation, emulation, and the broader verification lifecycle is a plus.\nTrack record of contributing to successful silicon tape-outs.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":4360,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-06T11:26:14Z"}],"visa":[],"liveness":{"score":47,"band":"ok","label":"Likely open","p_open":1,"p_active":0.777,"p_room":0.6,"age_days":74,"expected_fill_days":78,"reasons":["conf:3","velocity","win:late","crowd:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-tech-lead-formal-verification","json_url":"https://alion.io/job/astera-labs-tech-lead-formal-verification.json","meta":{"generated_at":"2026-10-17T09:16:34Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12191,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-tech-lead-formal-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-tech-lead-formal-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-tech-lead-formal-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-tech-lead-formal-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-tech-lead-formal-verification"}]}