{"id":462287,"url":"https://alion.io/job/astera-labs-tech-lead-verification-methodologycad","title":"Tech Lead– Verification Methodology/CAD","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":87,"open_postings":53,"ghost_share":0,"stale_share":0.302,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Leadership","role_family":"Leadership","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":37000,"max_usd":101000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":27},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Linux","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false},{"name":"UVM","optional":false},{"name":"CI/CD","optional":true},{"name":"GitLab CI","optional":true},{"name":"Jenkins","optional":true}],"status":"live","first_seen_at":"2026-08-27T19:32:18Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-17T22:26:52Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nTechLead- Verification Methodology / CAD / Automation Engineer \nExperience - 6-12 years \nJob Summary \nWe are looking for a Tech Lead - Verification Methodology/CAD/Automation Engineer to drive verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams. \nThe candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to establish efficient and reusable methodologies. \nKey Responsibilities \nOwn and drive verification methodology and infrastructure across projects. \nDevelop scalable frameworks for simulation, regression, coverage, debug, and verification signoff. \nBuild and maintain verification CAD/automation flows. \nDevelop automation scripts and tools using Python, Tcl, Perl, Shell, and/or C++. \nAutomate test generation, compilation, regression execution, result collection, coverage analysis, and reporting. \nDevelop infrastructure for large-scale UVM/SystemVerilog verification environments. \nImprove simulation and regression turnaround time through parallelization and optimization. \nIntegrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows. \nDevelop dashboards and metrics for verification quality, coverage, regression health, and project status. \nDebug infrastructure and tool-flow issues and provide rapid support to verification teams. \nEstablish reusable verification components, scripts, libraries, and methodology guidelines. \nDrive adoption of best practices across multiple verification teams. \nEvaluate new verification technologies and tools and recommend improvements. \nWork closely with EDA vendors to troubleshoot tool issues and improve flows. \nSupport migration and integration of new EDA tool versions and methodologies. \nDevelop documentation and training for verification teams. \nMentor verification CAD/methodology engineers and provide technical leadership. \nRequired Technical Skills \nStrong experience in verification methodology, CAD, and automation. \nStrong programming/scripting skills in Python, Tcl, Perl, Shell, and preferably C/C++. \nStrong understanding of SystemVerilog/UVM. \nExperience with simulation tools such as VCS, Xcelium, Questa, or equivalent. \nExperience building and maintaining regression infrastructure. \nStrong knowledge of coverage collection and analysis. \nUnderstanding of verification flows including: \nSimulation \nUVM \nLint \nCDC/RDC \nFormal \nCode/functional coverage \nRegression \nDebug \nStrong Linux/Unix environment experience. \nExcellent automation and problem-solving skills. \nPreferred Experience \nExperience with large-scale SoC/IP verification environments. \nExperience integrating multiple EDA tools into a unified verification flow. \nExperience with CI/CD infrastructure such as Jenkins, GitLab CI, or equivalent. \nExperience with distributed/parallel regression infrastructure. \nExperience with cloud-based or scalable compute environments. \nKnowledge of databases, dashboards, APIs, or web-based verification infrastructure is an advantage. \nExperience working with EDA vendors and managing tool-flow issues. \nLeadership Expectations \nAct as the technical owner for verification methodology and automation. \nIdentify opportunities to improve verification productivity, quality, and turnaround time. \nDefine and enforce verification methodology standards. \nMentor engineers and drive adoption of common frameworks. \nWork across multiple projects and teams to solve infrastructure challenges. \nStrong ability to balance immediate project requirements with long-term methodology improvements. \nEducation \nB.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, Computer Engineering, VLSI, or a related discipline. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":4899,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-06T11:26:14Z"}],"visa":[],"liveness":{"score":60,"band":"ok","label":"Likely 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