{"id":3651174,"url":"https://alion.io/job/astera-labs-technical-lead-digital-design-engineer","title":"Technical Lead Digital Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":50,"ghost_share":0,"stale_share":0.52,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":160000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"NVLink","optional":false},{"name":"Python","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-02T19:47:43Z","employer_posted_date":"2026-11-02","last_verified_at":"2026-11-04T19:15:54Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nOverview \nJoin our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'llwork on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. \nKey Responsibilities \nOwn the RTL implementation of complex digital designs from micro-architecture through sign-off. \nCollaborate with verification teams to review test plans and debug issues. \nSupport efforts to achieve timing closure and implement Design-for-Test (DFT) features. \nScripting and automation for ASIC methodologyimprovement. \nAccountable for quality and overall design success with the support of senior engineers. \nRequired Qualifications \nEducation & Experience: \nBachelor’s degree in electrical engineering or equivalent \n5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets \nDigital Design Expertise: \nExpertisein RTL coding with SystemVerilogand synthesis with Synopsys or Cadence. \nTrack recordof delivering high-qualitydigital designs from definition to production. \nExperience in high-speed design in advanced technology nodes. \nUnderstanding offunctional and formal verification at block and chip level. \nUnderstanding of clocking, CDC and RDCand static-timing analysis \nProtocols & Integration: \nProficientwith high-speed protocolssuch as PCIe, Ethernet, DDR, or similar \nExperience with IP development and integration \nTools & Methodologies: \nExpertisein design methodology, CAD automationor design infrastructure. \nProven SystemVerilogand Python expertisein a production environment \nFamiliarity with Synopsys and/or Cadence digital design flows \nBasic understanding of UVM-based verification methodologies \nProfessional Attributes: \nStrong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment \nGood communicationand collaboration skills; comfortable working cross-functionally with global teams \nSelf-directed learner who adapts quickly to changing requirements \nCustomer-focused mindset with the ability to prioritize and work independently to deliver high-qualitydesigns. \nPreferred Qualifications \nExperience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus \nKnowledge of design-for-test (DFT) in a production environment. \nBasesalary range is $160,000 USD-$200,000 USD,andwill be determinedbased on the candidate's capabilities and employees in similar positions. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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