{"id":462464,"url":"https://alion.io/job/astera-labs-technical-lead-physical-design-engineer","title":"Technical Lead Physical Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":80,"open_postings":54,"ghost_share":0,"stale_share":0.593,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-10T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":108000,"max_usd":188000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-07-01T21:48:47Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-12T06:01:44Z","board_verified":true,"closed_at":null,"days_open":102,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":102},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nAs an Astera Labs Technical Lead Physical Design Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.\nKey Responsibilities\nDrive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.\nDevelop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.\nDefine and manage I/O timing budgets across hierarchical designs.\nApply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.\nLeverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.\nProvide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.\nManage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.\nGenerate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.\nPartner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.\nBasic Qualifications\nBachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.\n≥5 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.\nExpertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.\nStrong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).\nProficiency with Cadence and/or Synopsys physical design/STA toolchains.\nStrong scripting ability (Tcl, Python, Perl).\nAbility to work independently with strong prioritization and a professional, customer-focused mindset.\nPreferred Experience\nFamiliarity with high-speed SERDES and Ethernet PHY timing challenges.\nKnowledge of ECO methodologies, DFT tools, and test coverage analysis.\nExperience working with IP vendors for both RTL and hard-macro integration.\nSystemVerilog/Verilog familiarity.\nThe base salary range is $140,000 CAD - $180,000.00 CAD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":3719,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-06T11:26:14Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 1","filings_12m":1,"filings_prev_12m":4,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":1}],"liveness":{"score":21,"band":"cold","label":"Long shot","p_open":1,"p_active":0.479,"p_room":0.44,"age_days":100,"expected_fill_days":78,"reasons":["conf:0","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-10T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-technical-lead-physical-design-engineer","json_url":"https://alion.io/job/astera-labs-technical-lead-physical-design-engineer.json","meta":{"generated_at":"2026-10-12T06:13:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9998,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-technical-lead-physical-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-technical-lead-physical-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-technical-lead-physical-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-technical-lead-physical-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-technical-lead-physical-design-engineer"}]}