{"id":2106122,"url":"https://alion.io/job/atom-computing-principal-asic-verification-engineer","title":"Principal ASIC Verification Engineer","company":{"id":1348,"name":"Atom Computing","domain":"atom-computing.com","url":"https://alion.io/company/atom-computing","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":88,"open_postings":4,"ghost_share":0,"stale_share":0.5,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-10-10T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":180000,"max":220000,"currency":"USD","period":"year","gross":null,"usd_annual":220000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-10-08T20:20:32Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-10-11T19:54:04Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"At Atom Computing, we build quantum computers using arrays of optically trapped neutral atoms that will empower customers to achieve unprecedented computational breakthroughs. Join a world-class team of scientists, engineers, and business professionals to advance the state-of-the-art in quantum computing.\nAtom Computing is seeking a Principal ASIC Verification Engineer to lead functional verification of ASICs used in our quantum computer. You will guide test-plan execution across engineers and contractors and contribute directly to testbench development, evaluation, and debug.\nResponsibilities\nOwn block-to-chip verification plans, schedules, and signoff criteria; lead test development and execution.\nProvide technical direction, mentor engineers, review test plans and code, and participate in candidate interviews.\nDefine contractor scope, milestones, and acceptance criteria; review deliverables and oversee integration and handoff.\nDevelop Python testbenches, reusable drivers, monitors, reference models, and scoreboards integrated with RTL simulators.\nImplement tests, automate regressions, debug failures, and close coverage. Communicate verification status, unresolved defects, and tapeout risks.\nLead post-layout gate-level verification, including netlist preparation, SDF annotation, and timing-accurate simulation.\nVerify test modes and patterns with DFT, design, and physical design teams; resolve timing and signoff issues.\nResolve requirements and interface issues with architecture, RTL, firmware, and hardware teams; support silicon bring-up and validation.\nPerform other duties as assigned.\nExperience & Education\nBachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience.\n10+ years of ASIC/SoC verification experience, with 15+ preferred.\nExperience verifying multiple ASICs through tapeout and subsequent silicon evaluation, applying findings to improve verification.\nQualifications\nExperience with block-to-chip verification of registers, data paths, and firmware interfaces.\nStrong Python skills for reusable, object-oriented testbenches with constrained-random stimulus, simulation control, checkers, and coverage.\nAbility to build behavioral models of mixed-signal blocks, including their digital interfaces and timing.\nExperience turning design requirements into verification plans, writing SystemVerilog assertions, and closing functional and code coverage.\nHands-on post-P&R experience preparing netlists and cell/memory models, annotating SDF, and debugging timing simulations.\nDFT verification experience with test modes and flows such as scan shift/capture, ATPG patterns, MBIST, or JTAG.\nStrong RTL and waveform debugging skills, especially resets, clock domains, X propagation, and timing checks.\nProficiency with SystemVerilog/UVM, HDL debug tools, Linux, and version control.\nExperience with regression automation, failure reproduction, and triage.\nPreferred Qualifications\nTechnical leadership through ASIC tapeout, including mentoring engineers, leading reviews, coordinating verification work, and communicating risks.\nExperience directing verification contractors, defining scope and acceptance criteria, and reviewing delivery against quality and schedule commitments.\nSilicon bring-up or validation experience, including lab debug and correlating hardware failures with simulation.\nExperience with formal verification, equivalence checking, CDC/RDC, lint, emulation, or FPGA prototyping.\nFamiliarity with real-time control, signal processing, or quantum hardware.","description_format":"text","description_chars":3582,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Quantum Computing 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