{"id":2043491,"url":"https://alion.io/job/attotude-digital-asic-design-engineer","title":"Digital ASIC Design Engineer","company":{"id":669247,"name":"AttoTude","domain":"attotude.com","url":"https://alion.io/company/attotude","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"D","score":53,"open_postings":14,"ghost_share":0.786,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-10T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":["Nuremberg, Germany"],"countries":["DE"],"hiring_countries":["US","DE","CA"],"hiring_countries_total":3,"salary":null,"salary_estimate":{"min_usd":92000,"max_usd":170000,"period":"year","method":"role_seniority_country_cell","sample_n":8},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-07T17:17:50Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-10T23:33:46Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":2},"description":"About the Role\nWe are seeking an experienced Digital IC Design Engineer to join our growing team. In this role, you will be part of an experienced design team developing cutting-edge DSP and mixed-signal ICs. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals.\nKey Responsibilities\nFlow system level requirements into Architecture and Design Specifications\nWork closely with Comm Systems Engineers to recommend implementation options for best power, performance, and area.\nDocument and write RTL code to meet system requirements\nWrite SystemVerilog testbenches and testcases to fully verify the design\nDevelop timing constraints, Synthesize the design and perform Static Timing Analysis and Timing Closure.\nPerform gate level simulations.\nSupport lab and HW/SW integration post-tapeout\nCollaborate with cross-functional teams to ensure timely project execution and design tape-outs\nStay updated with the latest trends and technologies in wideband high speed IC design and apply them to improve project outcomes\nOccasional travel to the Bay Area (<10%) for remote position\nQualifications\nRequired:\n5+ years of hands-on experience in CMOS (bulk and FinFET), digital IC design in various process technologies\nProven experience in strong coding/verification in SystemVerilog is required\nScripting language experience: Tcl, Python, and shell scripts required.\nBus interfaces: PCIe, AXI, UCIe, SPI, I2C, APB\nStrong communication and teamwork skills\nEducation:\nBachelor’s Degree in Electrical Engineering or related field is required\nMaster’s Degree in Electrical Engineering, Computer Engineering or a related field is preferred\nPreferred:\nExperience designing high speed Modems, SerDes, DSP blocks, FFTs, clock recovery, carrier recovery, digital filters, CTLE, DFE and MLSE.\nExperience matching and debugging Matlab models and vectors in RTL/gate level simulations.\nExperience working on a multidisciplinary team with Systems, RF, Mixed Signal, and SW engineers\nExperience with Cadence tools: XCelium, Genus, Tempus, Conformal, and Voltus\nExperience delivering IP blocks to internal and external customers\nAbility to drive innovation and implement new design methodologies.\nAbout Attotude\nAttoTude is at the forefront of revolutionizing data centers through advanced interconnect technology based on wired THz transceivers. By adapting the fiber from photonics and advancing today's ASICs to THz, our innovative AttoEngine eliminates networking bottlenecks, enabling high-speed interconnects for AI data centers. We are committed to overcoming existing networking bottlenecks to unleash the full potential of artificial intelligence.\nWhy Join Us\n· Work at the forefront of semiconductor research and innovation in digital communications.\n· Collaborate with a multidisciplinary team driving the next generation of THz technology\n· Access to state-of-the-art tools and processes at the leading-edge of ASIC development.\n· Competitive compensation, professional growth, and opportunities for scientific contribution.","description_format":"text","description_chars":3130,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"Germany","iso":"DE","kind":"country"},{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Network Equipment","Optical Communications"],"lifecycle":[{"event":"open","at":"2026-10-07T18:44:40Z"}],"visa":[],"liveness":{"score":60,"band":"ok","label":"Likely open","p_open":1,"p_active":0.602,"p_room":1,"age_days":2,"expected_fill_days":42,"reasons":["conf:2","stale_co","win:early"],"computed_at":"2026-10-10T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/attotude-digital-asic-design-engineer","json_url":"https://alion.io/job/attotude-digital-asic-design-engineer.json","meta":{"generated_at":"2026-10-11T03:43:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1672,"day_limit":5000,"remaining_today":3328,"minute_limit":60,"resets_at":"2026-10-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":669247},"rest":"https://alion.io/mcp/rest/get_company?id=669247"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fattotude-digital-asic-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fattotude-digital-asic-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fattotude-digital-asic-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/attotude-digital-asic-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fattotude-digital-asic-design-engineer"}]}