{"id":3548816,"url":"https://alion.io/job/attotude-dsp-integration-test-engineer","title":"DSP Integration Test Engineer","company":{"id":669247,"name":"AttoTude","domain":"attotude.com","url":"https://alion.io/company/attotude","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"C","score":65,"open_postings":17,"ghost_share":0.588,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Menlo Park, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":150000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"Bitbucket","optional":true},{"name":"Docker","optional":true},{"name":"GitHub","optional":true},{"name":"GitLab","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-30T17:31:08Z","employer_posted_date":"2026-10-30","last_verified_at":"2026-11-01T03:32:01Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":1},"description":"The Opportunity \nAttoTude'sworld-class engineering team works in a fast-paced, agile environment to develop next-generation baseband modems for intra-DCI applications. As a member of the system test team, the DSP Integration Test Engineer will own the bring-up, integration, and hardware maturity of high-speed DSPs coupled with AttoTude’sproprietary DiAxcable technology. The ideal candidate will be prepared to work with early prototypes, bringing up transmitand receiveDSP functions on hardwareand characterizingthe combined performance of AttoTude’s448Gbps/PAM4 AEC modules.A key componentof this role is the ability to understand and make tradeoffs across DSP, analog, and RF subsystems to optimizeoverall system performance and carry it through to volume production. The candidate should anticipatefrequent interactions with design engineers on signal processing and performance optimization. The role also includes designing, debugging, and optimizing firmware algorithms that maintainrobust performance over varying link conditions. \nRoles and Responsibilities \nThe successful candidate will play a pivotal role in bringing AttoTude'snext-generation communications platform from prototypesto volume production. Responsibilities include: \nHardware bring-up and maturationof high-speed DSP on prototype and production hardware, including transmitand receive data-path configuration, linkoptimization, troubleshootingand debug \nCharacterize and optimizeTx and Rx DSP blocks, including feed-forward and decision-feedback equalizers, MLSE, clock (timing) recovery, and assess their performance, complexity, and power tradeoffs \nMeasure high-speed DACs and ADCs (e.g., ENOB, SNDR, linearity, interleaving spurs, bandwidth, jitterand phase noise) and quantify their impact on modem SNR and BER \nDevelop calibration methods and transfer them to automated manufacturing test \nDevelop and test DSP-based control loops, including adaptation convergence, loop stability, tracking, and robustness over process, voltage, and temperature \nAnalyze link performance (pre-FEC BER, SNR) and correlate measurements with system models \nDevelop Python-based lab automation for test, characterization, and data analysis \nDrive performance validation and qualification, and transfer DSP configurations, calibrations, and test procedures to volume production \nThrough frequent interactionswith DSP design, DiAxcable design, firmware/controls, and hardware teams, you will feed experimental results back into architecture, designand manufacturabilitydecisions and help transition realized performance gains into the product. \nRequired Qualifications, Skills, and Experience \nMSEE minimum; PhD in Electrical Engineering or Applied Physics preferred, with specialization in high-speed electronic or electro-optic communication systems \nAt least 5 years of relevant industry experience with an MSEE, or at least 3 years with a PhD \nExperimental work experience in the bring-up and hardware maturity of high-speed DSPs, either coherent (e.g., QPSK, 16QAM, 64QAM) or multi-level PAM (e.g., PAM4) \nFoundational understanding of transmitand receive side DSP blocks, with emphasis on equalizers (e.g., FFE, DFE, MLSE) and their tradeoffs, and clock and carrier recovery \nPrior hands-on experimental experience measuring high-speed DACs and ADCs \nExperience developing calibration methods and transferring them to manufacturing test \nExperience developing and/or testing DSP-based control loops \nPerformance validation and productization experience, including transfer to volume production \nProficiencywith high-speed lab equipment such as real-time and sampling oscilloscopes, BERTs, arbitrary waveform generators, and spectrum and phase noise analyzers \nProgramming experience in Python and Matlabfor lab automation, modeling, and data analysis; C/C++ a plus \nExcellent written and oral communication skills, including the ability to communicate complex information clearly and concisely across multiple platforms and modalities \nResourceful collaborator, supporting teammates and colleagues as needed \nPreferred Qualifications \nPrior work experience with coherent optical modules or 224 Gbps/PAM4 AEC modules \nFamiliarity with related industry standards (e.g., OIF 400ZR/800ZR, OIF CEI-224G, IEEE 802.3dj) \nUnderstanding of forward error correction (e.g., RS/KP4, soft-decision FEC) and its interaction with DSP performance \nExperience characterizing RF and mm-wave components (e.g., S-parameters, nonlinear compression) and modeling linear and nonlinear signal impairments \nFamiliarity with module management and telemetry interfaces (e.g., CMIS) and firmware-based monitoring \nFamiliarity with RTL/Verilog or hardware-oriented algorithm implementation \nFluent with statistical analysis methods and software repositories (e.g., GitHub, GitLab, Bitbucket, Docker)\nAnnual Salary Range\n$150,000—$250,000 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