{"id":3386210,"url":"https://alion.io/job/attotude-eda-and-cad-lead-engineer-manager","title":"EDA and CAD Lead Engineer / Manager","company":{"id":669247,"name":"AttoTude","domain":"attotude.com","url":"https://alion.io/company/attotude","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"C","score":63,"open_postings":16,"ghost_share":0.625,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Menlo Park, United States"],"countries":["US"],"hiring_countries":["US"],"hiring_countries_total":1,"salary":{"min":140000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false}],"status":"live","first_seen_at":"2026-10-28T04:18:59Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-11-04T21:39:05Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":7},"description":"We are seeking an experienced EDA/CAD lead engineer to join our growing team. In this role, you will be part of the experience design and layout team to develop cutting-edge mixed-signal ICs. You will be involved in the technical aspects of the ASIC design and development, from concept through to production. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals. \nKey Responsibilities: \nFloor planning, IP integration \nPad Ring creation \nWork with analog/mixed-signal designers for high-performance layout integration \nWork with digital designers for DFT/ATPG/Scan logic integration \nPerform LVS/DRC checks and fix issues \nIntegration of Digital/RF/mmWave blocks into IC Top Level \nCollaborate with cross-functional teams to ensure timely project execution and design tape-outs \nStay updated with the latest trends and technologies in wideband high speed IC design and apply them to improve project outcomes \nOccasional travel to the Bay Area (<20%) for remote position \nQualifications: \n5+ years of hands-on experience in CMOS (bulk and advanced FinFET) IC implementation in multiple process technologies \nStrong experience with Cadence (and various EDA) tools is required (Virtuoso, Calibre, Voltus) \nExperience in multiple dedicated tapeout support is required \nScripting language experience in Tcl, Python, Perl, Makefile, and shell scripts are required \nEducation: \nFormal Cadence digital layout training or certification is required \nBachelor’s degree in electrical engineering, computer science or a related field is preferred \nPreferredSkills: \nExperience with CMOS, and/or SiGe Process Development Kits \nExperience working on a multidisciplinary team with RF/Mixed Signal, Hardware, Firmware, and Software engineers \nStrong communication and teamwork skills \nExperience working in fast-paced environments with a strong track record of delivering high-quality designs on time. \nBenefits : \nCompetitive salary \nStock options plan \nPaid time off \nHealth benefits \nAnnual Salary Range\n$140,000—$200,000 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