{"id":661747,"url":"https://alion.io/job/axiado-asic-design-engineer","title":"ASIC Design Engineer","company":{"id":178091,"name":"Axiado","domain":"axiado.com","url":"https://alion.io/company/axiado","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"A","score":95,"open_postings":50,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":142,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18500,"max_usd":47000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bitbucket","optional":false},{"name":"Jenkins","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-05-13T22:13:41Z","employer_posted_date":"2026-05-13","last_verified_at":"2026-10-17T17:30:52Z","board_verified":true,"closed_at":null,"days_open":156,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":156},"description":"Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure-from data centers to next generation cloud and AI platforms-by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems.\nFounded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.\nAt Axiado, developing breakthrough technology takes more than great engineering-it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.\nIf you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey.\nASIC/SoC Design position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture. As the ASIC/SoC Design Engineer for Axiado, you will have the opportunity to work in all areas of the SoC design flow. You will work closely with the Architecture, Verification, Physical Design and Software teams, and report to the Director of Engineering.\nKEY RESPONSIBILITIES\nHelp develop the design and implementation of SoCs.\nMicro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;\nTop-level and block-level performance, bandwidth, and power optimization;\nWork with FPGA engineers to perform early prototyping; and\nSupport test program development, chip validation, and chip life until production maturity.\nCollaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.\n 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization;\nProficient in writing clear, implementable micro-architecture specifications;\nExpertise in writing efficient RTL code in Verilog and SoC integration\nGood understanding of assertions, coverage analysis, RTL synthesis, and timing closure;\nShould have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.\nExperience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce.\nFluency with scripting languages (e.g., Perl, Python);\nMust have gone through at least one tapeout.\nPreferred: Silicon bring-up and debug experience\nExperience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.\n Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.\nWe are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.\nAxiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. 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