{"id":2422928,"url":"https://alion.io/job/axiado-senior-emulation-engineer","title":"Senior Emulation Engineer","company":{"id":178091,"name":"Axiado","domain":"axiado.com","url":"https://alion.io/company/axiado","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"A","score":95,"open_postings":53,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":106,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":43000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Palladium","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"RTOS","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-13T05:37:41Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-14T14:12:35Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":1},"description":"Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure-from data centers to next generation cloud and AI platforms-by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems.\nFounded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.\nAt Axiado, developing breakthrough technology takes more than great engineering-it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.\nIf you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey.\nThe Senior Emulation Engineer position is your opportunity to join one of the industry’s leading companies in platform security management and ransomware detection for cloud datacenters, 5G infrastructure and disaggregated compute ecosystems. We are looking for an emulation engineer to run and debug system-level workloads on Synopsys ZeBu emulation platforms and to own the integration and bring-up of transactors (XTORs) that connect the emulated SoC to real and virtual interfaces. Your focus is what happens once the design is running: getting the interfaces alive, executing firmware, OS, and use-case validation, triaging failures, and finding issues before silicon. This role is critical for validating the interoperability of our design with commercial AI servers, and for bridging the gap between hardware and software, as well as supporting SW development.\nKey Responsibilities :\nRuntime validation\nExecute and debug system-level tests, firmware, and software workloads on ZeBu emulation models\n\nBring up and validate secure boot flows (ROM, bootloader, Linux/RTOS) and platform security features such as root of trust, attestation, and firmware update on the emulated SoC\n\nDevelop and run use-case scenarios covering platform security management, ransomware detection workloads, and datacenter/5G traffic patterns\n\nTriage failures and isolate root cause across RTL, firmware, driver, testbench, XTOR, and emulation environment; produce clear, reproducible bug reports\n\nUse ZeBu runtime debug capabilities (waveform capture, triggers, memory/register access, checkpoint/restore, force/release) to debug efficiently at speed\n\nRun and manage long-running regressions and soak tests; track pass rates, failure trends, and run-to-run stability\n\nPerform power-aware and performance validation runs: activity capture, bandwidth/latency profiling, and use-case benchmarking\n\nXTOR integration and bring-up\nIntegrate and configure ZeBu transactors and speed adapters (PCIe, CXL, Ethernet, NVMe, DDR/LPDDR, I2C/I3C/SMBus, SPI, UART, JTAG, etc.) at the testbench and runtime level\n\nBring up XTOR-to-DUT links from first connectivity through link training, enumeration, and stable data traffic; resolve protocol-level and configuration issues\n\nDevelop host-side software and drivers that control XTORs (C/C++, Python, SystemVerilog DPI, ZeBu API), including connections to real devices, virtual peripherals, or hybrid platforms\n\nDebug XTOR-related failures using protocol analyzers, waveforms, and logs; determine whether the issue lies in the DUT, the XTOR, clocking/speed-adapter configuration, or the host\n\nTune XTOR configuration for throughput, latency, and emulation-frequency compatibility\n\nMaintain XTOR configuration, version control, and documentation across model releases\n\nConfigure host servers, boot environments to interact with the emulated design\n\nIntegrate, develop and debug transactors, bridges and protocol adapters as needed\n\nDebug and root-cause embedded HW, SW and test failures in emulation\n\nCollaborate with RTL, DV and SW teams to resolve system level bugs\n\n BS or MS degrees or higher in EE, CE or related fields\n\n7+ years of hands-on experience in prototyping, emulation, SOC design and validation\n\nSelf-driven, good problem solving and communication skills\n\nHands-on experience running and debugging designs on Synopsys ZeBu (or comparable emulators such as Palladium or Veloce), including runtime control (NGTB or C based), waveform capture, and checkpoint/restore\n\nExperience integrating and debugging high-speed and low-speed interfaces\n\nFamiliarity with embedded software bring-up and bootloader/kernel interactions\n\nProficiency with scripting languages (Python, Perl, TCL) for automation\n\nPreferred qualifications include: experience in design verification, hardware/software co-simulation, Linux device drivers, bare-metal FW or boot loaders\n\n Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.\nWe are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.\nAxiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. 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