{"id":661706,"url":"https://alion.io/job/axiado-senior-lead-physical-design-engineer","title":"Senior / Lead Physical Design Engineer","company":{"id":178091,"name":"Axiado","domain":"axiado.com","url":"https://alion.io/company/axiado","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"A","score":95,"open_postings":43,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":147,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":46000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Shift-Left Security","optional":false},{"name":"Synopsys IC Validator","optional":false},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-08-04T11:21:46Z","employer_posted_date":"2026-08-04","last_verified_at":"2026-10-29T07:07:39Z","board_verified":true,"closed_at":null,"days_open":85,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":85},"description":"Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure-from data centers to next generation cloud and AI platforms-by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems.\nFounded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.\nAt Axiado, developing breakthrough technology takes more than great engineering-it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.\nIf you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey.\n We are looking for a highly experienced and hands-on Senior / Lead Physical Design Engineer to drive backend implementation, signoff quality, methodology development, and project execution across our ASIC programs.\nThis role combines technical leadership with hands-on execution. The successful candidate will be responsible for defining implementation strategies, establishing Physical Design and Physical Verification methodologies, reviewing and guiding work performed by contractors and external vendors, and ensuring successful execution from RTL handoff through tapeout.\nThe ideal candidate is a strong shift-left thinker who can proactively identify implementation risks, influence architectural decisions, and drive scalable solutions while remaining deeply involved in technical problem solving.\nKey Responsibilities\nTechnical Leadership & Project Execution\nLead Physical Design activities from project planning through tapeout.\n\nDefine implementation strategies, milestones, and execution plans.\n\nWork closely with contractors, consultants, and external implementation partners to ensure high-quality deliverables.\n\nReview implementation progress, identify risks, and drive corrective actions.\n\nProvide technical leadership across Physical Design, STA, DFT, RTL, and CAD teams.\n\nDrive design reviews and implementation readiness reviews.\n\nPhysical Design Ownership\nOwn block and full-chip implementation activities including:\n\nFloorplanning\n\nPower Planning\n\nPlacement\n\nCTS\n\nRouting\n\nTiming Closure\n\nECO Implementation\n\nSignoff Closure\n\nDrive performance, power, area, congestion, and timing optimization.\n\nPhysical Verification & Signoff\nDefine and drive signoff methodology and closure strategy.\n\nLead DRC, LVS, ERC, Antenna, Density, and Manufacturing rule closure.\n\nReview and sign off vendor deliverables related to physical verification.\n\nDebug complex signoff issues and drive root-cause resolution.\n\nMethodology & Flow Development\nDevelop and improve Physical Design methodologies, implementation recipes, and signoff flows.\n\nDrive automation initiatives to improve productivity and design quality.\n\nEstablish best practices, checklists, and execution guidelines across projects.\n\nPromote shift-left methodologies to improve backend predictability and reduce project risk.\n\nCross-Functional Collaboration\nPartner with Architecture, RTL, DFT, Verification, Packaging, CAD, and Product teams.\n\nInfluence design decisions through implementation-aware feedback.\n\nDrive early risk identification and mitigation planning.\n\nSupport customer, vendor, and management reviews when required.\n\n Required Qualifications\nBS/MS in Electrical Engineering or related field.\n\n8-12 years of ASIC Physical Design experience.\n\nMultiple successful tapeouts in advanced technology nodes.\n\nStrong experience owning implementation from RTL handoff through GDS signoff.\n\nExperience leading projects, reviewing deliverables, and coordinating work across multiple stakeholders.\n\nStrong Expertise In\nFloorplanning & Hierarchical Planning\n\nPower Planning\n\nPlacement & Optimization\n\nCTS & Clock Architecture\n\nRouting & Signal Integrity\n\nSTA & Timing Closure\n\nECO Methodologies\n\nMCMM Flows\n\nPower Optimization\n\nLow Power Design Techniques\n\nPhysical Verification Expertise (Must Have)\nStrong hands-on experience with:\n\nCalibre\n\nIC Validator (ICV)\n\nExpertise in:\n\nDRC\n\nLVS\n\nERC\n\nAntenna\n\nDensity Closure\n\nPhysical Signoff\n\nAbility to independently debug and resolve complex signoff issues.\n\nPreferred Qualifications\nExperience managing or mentoring junior engineers, contractors, or external vendors.\n\nStrong Tcl and Python scripting skills.\n\nExperience developing implementation methodologies and signoff frameworks.\n\nExperience with advanced nodes (7nm/5nm/3nm and below).\n\nFamiliarity with low-power implementation and UPF flows.\n\nExperience with package-aware floorplanning and bump planning.\n\nAll your information will be kept confidential according to EEO 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