{"id":2332093,"url":"https://alion.io/job/axiado-senior-system-level-verification-engineer-2","title":"Senior System Level Verification Engineer","company":{"id":178091,"name":"Axiado","domain":"axiado.com","url":"https://alion.io/company/axiado","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":{"grade":"A","score":95,"open_postings":50,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":106,"computed_at":"2026-10-12T06:55:09Z"}},"role":"DevOps","role_family":"DevOps","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":38000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":38},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Confluence","optional":false},{"name":"Jira","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-12T06:39:59Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-12T15:51:59Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure-from data centers to next generation cloud and AI platforms-by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems.\nFounded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.\nAt Axiado, developing breakthrough technology takes more than great engineering-it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.\nIf you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey.\n Design Verification Technical Team Lead position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IOT.\nYou will be responsible for chip level verification of complex ARM based SOC HW, debugging, and ROM and FW bringup.\nKey Responsibilities\nDevelop SOC system level test environment for simulation and emulation, including log generation, backdoor configuration and device modeling\n\nDevelop testplan and tests, including error condition tests and stress tests\n\nRun and debug tests in regressions, both in simulation and on emulator\n\nWork with other teams in root-causing HW issues, and creating system level test cases for them\n\nValidation ROM\n\nWork with SW team in debugging device driver issues, and OS boots\n\n7 years of DV or validation experience, and 5 years of system Level verification experience using C\n\nHas worked through complete project cycle of an SOC ASIC chip\n\nThorough understanding of CPU and its debug architecture, as well as SOC system architecture\n\nProficient in programming and modeling typical SOC connected devices, such as JTAG, UART, SPI, I2C.\n\nProficient in testplanning, test case development using C, and self checking in such tests\n\nProficient in RTL debugging using waveform viewer\n\nMastery in C programming, and fluent in scripting languages such as Make, Python, Perl and shell script\n\nFluent in documentation and issue tracking using Confluence and Jira tools\n\nPreferred experience in\nValidation on emulation, FPGA and post-silicon\n\nComplex IP interface validation of USB, Ethernet, PCIE, DDR\n\nUsing AI tools in testplanning, generation and debugging\n\n Experience with SPDM, PLDM, MCTP protocols\nExperience with Caliptra, Crypto/security APIs\nExperience with bootloaders and platform firmware, including initialization, boot flows, reset handling, recovery, and firmware-update mechanisms.\nUnderstanding of firmware authentication/signature verification, OTP provisioning","description_format":"text","description_chars":3819,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-12T09:16:09Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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