{"id":728300,"url":"https://alion.io/job/ayosemi-principal-fpga-engineer","title":"Principal FPGA Engineer","company":{"id":669389,"name":"Ayo Semiconductor","domain":"ayosemi.com","url":"https://alion.io/company/ayosemi","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"B","score":75,"open_postings":4,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Boston, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":140000,"max_usd":262000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":335},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Embedded C","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"C","optional":true}],"status":"live","first_seen_at":"2026-08-24T18:47:35Z","employer_posted_date":"2026-08-24","last_verified_at":"2026-10-02T09:27:59Z","board_verified":true,"closed_at":null,"days_open":39,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":39},"description":"About Ayo\nAyo is a venture-backed early-stage startup that will radically redefine how humanity performs compute for AI. Our photonic processors will provide orders of magnitude improvement in speed and power efficiency in comparison to conventional digital compute platforms by taking advantage of the natural parallelism, speed and energy efficiency of light.\nThe Role\nWe are looking for a Principal FPGA Engineer to join our hardware team. You will write and deploy code to FPGAs that are central to our chip development and verification workflow. This is hands-on work with real hardware - you will move fast, own your work end to end, and collaborate closely with our AI and hardware teams to keep our prototype development moving.\nThis is a fully onsite role based in Boston. This is a fully onsite role based in Boston. Candidates must be authorized to work in the United States; we cannot sponsor visas for this role.\nWhat You'll Do\nDesign, implement, and test FPGA-based systems that support our chip verification and prototype development pipeline.\n\nDeploy and iterate on RTL code (Verilog or VHDL) targeting FPGAs in our prototype hardware.\n\nDeploy and iterate on embedded C/C++ code targeting embedded processors on FPGA system-on-chips\n\nSupport the hardware team by performing FPGA trade studies and assessing the viability of proposed pin mappings on developmental circuit card assemblies\n\nSupport bring-up and test of new printed circuit boards and prototypes by writing and testing interfaces to peripherals such as ADCs, DACs, memory, etc.\n\nWork closely with ASIC engineers to build test benches to test ASICs and to bring up and test prototypes of our computing systems..\n\nContribute to upgrading and scaling our existing FPGA infrastructure as we grow.\n\nWhat We're Looking For\nRTL proficiency required - Verilog or VHDL. This is the foundation of the role.\n\nReal industry FPGA experience - we want to see that you have deployed code to real hardware, not just completed academic coursework projects.\n\nStrong general programming ability, in addition to RTL.\n\nFamiliarity with major FPGA platforms - Xilinx/AMD experience is preferred; Lattice or Intel/Altera is also fine.\n\nEmbedded systems experience is a plus - ADC/DAC interfaces, working with real-world signals.\n\nAny exposure to ASIC verification workflows is a bonus - if you've sat next to a chip design and used FPGAs to validate it, we want to hear about it.\n\nUndergraduate or Master's degree - a PhD is not required. We care about what you've built, not the credential.\n\nWhy Ayo\nYou'll be the first FPGA engineer on the team - your work will directly shape how we validate our chips and build our prototypes.\n\nWe are working on a genuinely hard and interesting problem: unseating the GPU as the dominant AI compute platform.\n\nEarly-stage means real ownership, real impact, and meaningful equity.\n\nCompetitive salary. Equity commensurate with stage and seniority. Benefits package including health, dental, and vision.\n\nFully onsite in Boston - we are a collaborative, in-person team.","description_format":"text","description_chars":3061,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-09-11T09:06:38Z"}],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.592,"p_room":0.55,"age_days":38,"expected_fill_days":31,"reasons":["conf:19","win:tail"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/ayosemi-principal-fpga-engineer","json_url":"https://alion.io/job/ayosemi-principal-fpga-engineer.json","meta":{"generated_at":"2026-10-03T00:52:39Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":621,"day_limit":5000,"remaining_today":4379,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}