{"id":729055,"url":"https://alion.io/job/baidu-senior-rtl-design-engineer","title":"Senior RTL Design Engineer","company":{"id":101,"name":"Baidu","domain":"baidu.com","url":"https://alion.io/company/baidu","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"C","score":55,"open_postings":28,"ghost_share":0.75,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":129000,"max_usd":241000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":910},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Chisel","optional":true},{"name":"Scala","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true},{"name":"VHDL","optional":true}],"status":"live","first_seen_at":"2022-08-22T18:14:16Z","employer_posted_date":"2026-04-28","last_verified_at":"2026-10-01T08:52:35Z","board_verified":true,"closed_at":null,"days_open":1500,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":1500},"description":"Responsibilities: \n\nArchitect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators. \n\nMicroarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design. \n\nPerform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans. \n\nWork with physical implementation team to implement and optimize physical design to meet frequency, area, power goals. \n\nCollaborate with performance modelling team for performance exploration and optimization to meet performance goals. \nRequirements: \n\n8+ yrs of recent industry experience in high-performance, energy-efficient CPU designs. \n\nExpertise in CPU processor designs in one or more of the following areas: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; scalar and/or vector execution units; load-store unit; cache and memory subsystems. \n\nKnowledge of RISC-V architecture is a plus. \n\nProficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL. \n\nExperience with Scala and/or Chisel is a plus. \n\nAttention to detail and a focus on high-quality design. \n\nAbility to work well with others and a belief that engineering is a team sport. \n\nKnowledge of at least one object-oriented and/or functional programming language. \n\nBackground of successful CPU development from architecture through tapeout.\n\nMS/ PhD degree in EE, CE, CS or a related technical discipline, or equivalent experience.","description_format":"text","description_chars":1604,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Advertising","Autonomous Driving","Cloud Platforms (IaaS & PaaS)","Foundation Models"],"lifecycle":[{"event":"open","at":"2026-09-11T09:21:30Z"}],"liveness":{"score":4,"band":"cold","label":"Long shot","p_open":1,"p_active":0.133,"p_room":0.28,"age_days":1500,"expected_fill_days":24,"reasons":["conf:11","stale_co","ghost","win:tail","crowd:"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/baidu-senior-rtl-design-engineer","json_url":"https://alion.io/job/baidu-senior-rtl-design-engineer.json","meta":{"generated_at":"2026-10-01T17:58:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":217,"day_limit":5000,"remaining_today":4783,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}