{"id":3678087,"url":"https://alion.io/job/barco-lead-verification-engineer","title":"Lead Verification Engineer","company":{"id":1769262,"name":"Barco","domain":"barco.com","url":"https://alion.io/company/barco-com","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career sitemap","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":14,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verification & Validation","optional":false},{"name":"CI/CD","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-11-03T11:59:46Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-04T12:27:10Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Purpose of the Job\nThe Lead Verification Engineer will lead and drive the verification and validation of complex digital video and high-speed communication systems, from block-level verification through FPGA implementation and complete system integration.\nThe position requires 14+ years of relevant industry experience and strong hands-on expertise in HDMI, DVI, SDI, SystemVerilog/UVM, directed verification, Gate-level simulation, high-speed digital interfaces, system integration and hardware debugging.\nThe Lead Verification Engineer is expected to combine strong verification methodology with practical system-debugging skills and take technical ownership of verification strategy, execution, coverage, debugging, and verification closure.\nKey Responsibilities\nIn This Role, You Will\nLead the verification strategy, architecture, planning and execution based digital products and subsystems.\nDefine comprehensive verification plans, test scenarios, verification environments, functional coverage goals and sign-off criteria.\nDevelop and maintain reusable SystemVerilog/UVM verification environments, including testbenches, drivers, monitors, scoreboards, sequences, assertions and functional coverage.\nDevelop directed and constrained-random tests to verify complex functional scenarios and corner cases.\nLead verification of professional digital-video interfaces and video-processing systems, particularly HDMI, DVI, SDI etc\nVerify video-related functions across resolutions, frame rates, colour formats, bit depths, timing conditions and abnormal/error scenarios.\nPerform verification of complex designs, including custom RTL, IP, clocking, reset, memory and high-speed interface subsystems.\nDevelop and execute gate-level simulations (GLS) and investigate failures involving timing, initialisation, reset, X-propagation and implementation effects.\nPerform system-level integration, verification and debugging, hardware, firmware, embedded software and host software.\nProfile\nEducation and Experience\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, VLSI, Embedded Systems, or a related discipline.\n14+ years of hands-on industry experience in verification, digital design verification and system-level verification.\nDemonstrated experience taking technical ownership of complex verification activities.\nPreferred Skills\nExperience with professional video-processing, broadcast, entertainment or high-performance visualisation systems.\nExperience in real-time video and image processing.\nStrong knowledge of CDC/RDC verification.\nExperience with scripting and automation using Python, Tcl, Shell or similar languages.\nExperience with continuous integration and automated regression environments.\nKnowledge of timing constraints and static timing analysis.\nExperience debugging interactions between RTL, embedded processors and external high-speed devices.\nExperience correlating simulation failures with hardware observations.\nFamiliarity with board-level high-speed digital design concepts and signal integrity is advantageous.","description_format":"text","description_chars":3091,"description_truncated":false,"requirements":{"experience_years_min":14,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Pro AV & Digital Signage","Displays & Panel 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