{"id":2755044,"url":"https://alion.io/job/biren-technology-soc-arch","title":"SoC Arch","company":{"id":47989,"name":"Biren Technology","domain":"birentech.com","url":"https://alion.io/company/biren-technology","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Moka","truth_index":{"grade":"B","score":75,"open_postings":11,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shanghai, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":33000,"max_usd":97000,"period":"year","method":null,"sample_n":3689},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Apache TVM","optional":false},{"name":"C++","optional":false},{"name":"CUDA","optional":false},{"name":"CUDA Toolkit","optional":false},{"name":"DirectX","optional":false},{"name":"HPC","optional":false},{"name":"MLIR","optional":false},{"name":"NVLink","optional":false},{"name":"OpenCL","optional":false},{"name":"Python","optional":false},{"name":"PyTorch","optional":false},{"name":"PyTorch C++","optional":false},{"name":"ROCm","optional":false},{"name":"SystemC","optional":false},{"name":"Triton","optional":false},{"name":"XLA","optional":false}],"status":"live","first_seen_at":"2026-08-26T09:43:02Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-17T05:40:25Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"GPGPU SoC 架构师 / Senior SoC Architect\n岗位概述\n资深 SoC 架构师，负责面向\nGPGPU / AI 加速器芯片的 SoC 平台架构定义、关键\nIP 选型、代际演进规划、性能建模与系统级技术决策。\n该岗位将深度参与从产品需求定义、architecture exploration、IP evaluation、SoC specification、RTL implementation support、verification\nstrategy 到 silicon bring-up / performance tuning 的完整芯片研发周期。候选人需要具备从 workload、software stack、system architecture 到 SoC microarchitecture 的完整视角，能够在性能、功耗、面积、成本、风险和产品上市时间之间做系统性权衡。\n岗位职责\nl 负责 GPGPU / AI Accelerator SoC 顶层架构定义，包括\ncompute subsystem、CPU subsystem、memory subsystem、NoC / interconnect、IO subsystem、security、RAS、power management、debug / trace、boot / firmware 等关键模块规划。\nl 主导 SoC 关键 IP 的选型、评估和集成策略，包括 CPU IP、NoC / fabric、PCIe / CXL controller、HBM / GDDR / DDR\nmemory controller、IOMMU / SMMU、security\nIP、RAS IP、power management IP、debug / trace IP 等。\nl 建立 IP selection methodology，从 performance、power、area、latency、bandwidth、QoS、coherency、scalability、verification complexity、software ecosystem、vendor support、license cost、integration risk 和长期可演进性等维度进行技术评估。\nl 规划 SoC IP roadmap 和平台演进路线，定义不同产品代际之间的 IP 复用、升级、替换和自研策略，支撑未来 2-3 代 GPGPU / AI 芯片产品演进。\nl 负责 SoC interconnect 架构设计，包括 AXI / ACE / CHI /\nCXL / PCIe / NoC 等协议和互连方案选型，定义带宽规划、QoS 策略、仲裁机制、地址映射、memory ordering、cache coherency 和 deadlock avoidance 方案。\nl 负责 memory subsystem 架构定义与优化，包括 HBM / GDDR /\nDDR 控制器、cache hierarchy、MMU /\nIOMMU、TLB、memory partition、channel interleaving、ECC / RAS、memory virtualization、page migration 等关键机制。\nl 针对 AI training / inference、HPC、graphics、cloud GPU、multi-tenant\nGPU 等 workload 进行性能建模、trace\nanalysis 和瓶颈分析，指导 NoC、cache、memory bandwidth、DMA engine、command processor、scheduler 和 IO bandwidth 等架构参数优化。\nl 负责每一代 GPGPU SoC 的架构演进分析，包括 process node、HBM generation、PCIe / CXL generation、NoC topology、cache hierarchy、memory capacity / bandwidth、chiplet\npartition、die-to-die interconnect、power delivery、RAS 和\nvirtualization capability 等方向。\nl 与 GPU Core、Compiler、Driver、Runtime、Firmware、RTL、Verification、Physical Design、Packaging、Board、System\nSoftware 和 Product 团队紧密协作，确保架构方案可实现、可验证、可调优、可量产。\nl 与外部 IP vendor、EDA vendor 和生态伙伴协作，完成 IP technical assessment、interface\nrequirement definition、integration risk review、performance target alignment 和 bring-up\nissue closure。\nl 定义 SoC 级低功耗和功耗管理架构，包括 clock / power domain 划分、DVFS、power gating、thermal\nthrottling、power telemetry、power\ncapping 和 performance per watt 优化策略。\nl 参与芯片 bring-up、性能调优和量产问题定位，基于 silicon data、profiling data、validation feedback、customer workload 和上一代产品 lessons learned，推动下一代 SoC 架构改进。\nl 输出高质量架构文档和规格，包括 SoC architecture spec、IP selection report、IP roadmap、memory map、interface spec、QoS spec、performance model report、power management\nspec、RAS spec、virtualization\nspec 等。\n任职要求\nl 电子工程、计算机体系结构、微电子、计算机科学等相关专业本科及以上学历，硕士或博士优先。\nl 8 年以上 SoC / GPU / AI Accelerator / CPU / DPU\n/ NPU / Network Processor / High-performance ASIC 架构、设计或系统分析经验，具备复杂芯片量产经验者优先。\nl 深入理解复杂 SoC 架构，包括 interconnect、memory subsystem、cache coherency、DMA、interrupt、virtualization、security、boot flow、power\nmanagement、debug / trace、RAS 等。\nl 熟悉 AMBA 协议体系，如 AXI / ACE / CHI; 熟悉 PCIe、CXL、CCIX、NVLink、Infinity Fabric、UCIe 或类似高速互连 / die-to-die interconnect 者优先。\nl 熟悉 GPGPU / AI accelerator 架构，理解 SIMT / SIMD、warp / wavefront、cache hierarchy、shared memory、tensor core / matrix engine、command processor、scheduler、memory coalescing 等概念。\nl 具备关键 SoC IP 选型、供应商评估、技术谈判或 IP 集成经验，理解 commercial IP 与 in-house IP 在性能、风险、成本、可控性、验证复杂度和长期演进上的取舍。\nl 熟悉主流 SoC IP 生态，包括 ARM / RISC-V CPU、Arteris / ARM CMN / Synopsys NoC、Synopsys /\nCadence / Rambus memory controller、PCIe / CXL\ncontroller、IOMMU / SMMU、security\nIP、debug / trace IP 等。\nl 熟悉 HBM / GDDR / DDR memory system，理解 memory\nbandwidth、latency、bank conflict、channel interleaving、page policy、ECC / RAS、memory protection 和 memory virtualization 等机制。\nl 具备扎实的性能分析和建模能力，能够使用 C++ / Python / SystemC / gem5 / proprietary simulator 等进行 architecture modeling、traffic modeling、trace analysis、performance projection 和 design space exploration。\nl 理解 GPU 软件栈和系统软件对 SoC 架构的影响，包括 driver、runtime、firmware、compiler、OS kernel、IOMMU、virtual memory、scheduling、telemetry 和 debug infrastructure。\nl 具备跨团队技术推动和架构决策能力，能够在架构、RTL、验证、软件、后端、封装、产品和外部 IP vendor 之间推动复杂技术问题闭环。\nl 具备优秀的中英文技术沟通和文档能力，能够输出清晰、严谨、可执行的架构规格和技术决策文档。\n加分项\nl 有GPGPU公司相关工作经验。\nl 参与过 Data Center GPU、AI Training / Inference\nAccelerator、HPC Accelerator、High-end\nSoC、DPU、NPU、Chiplet 或 2.5D / 3D 封装产品架构定义。\nl 熟悉 GPU software ecosystem，包括 CUDA、ROCm、OpenCL、Vulkan、DirectX、MLIR、TVM、XLA、PyTorch backend、Triton\n等。\nl 熟悉云端 GPU 虚拟化和资源隔离场景，包括 SR-IOV、MIG-like partition、IOMMU、ATS / PRI / PASID、memory isolation、QoS isolation、secure multi-tenancy 等。\nl 熟悉 Chiplet、HBM integration、UCIe、BoW、AIB、die-to-die interconnect、advanced packaging、interposer 和 silicon interposer / organic\nsubstrate 相关架构约束。\nl 熟悉 RAS / Safety / Security 架构，包括 ECC、parity、poison、retry、scrubbing、secure boot、root of trust、TEE、firewall、memory encryption、attestation 等。\nl 有从前一代产品 silicon data / customer workload / profiling data 反推下一代 SoC 架构演进的经验。","description_format":"text","description_chars":4883,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"German","level":"Advanced (C1)","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Artificial Intelligence"],"lifecycle":[{"event":"open","at":"2026-10-17T01:30:47Z"}],"visa":[],"liveness":{"score":10,"band":"cold","label":"Long shot","p_open":1,"p_active":0.275,"p_room":0.35,"age_days":51,"expected_fill_days":22,"reasons":["conf:0","stale_co","win:tail"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/biren-technology-soc-arch","json_url":"https://alion.io/job/biren-technology-soc-arch.json","meta":{"generated_at":"2026-10-17T08:22:33Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11318,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":47989},"rest":"https://alion.io/mcp/rest/get_company?id=47989"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fbiren-technology-soc-arch"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fbiren-technology-soc-arch"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fbiren-technology-soc-arch"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/biren-technology-soc-arch\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fbiren-technology-soc-arch"}]}