{"id":522873,"url":"https://alion.io/job/bitdeer-technologies-group-seniorstaff-mid-end-engineer-3dprocess-integration","title":"Senior/Staff Mid-End Engineer (3D/Process Integration)","company":{"id":174995,"name":"Bitdeer Technologies Group","domain":"bitdeer.com","url":"https://alion.io/company/bitdeer","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Breezy","truth_index":{"grade":"B","score":79,"open_postings":13,"ghost_share":0,"stale_share":0.846,"repost_share":0,"time_to_fill_p50_days":39,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Semiconductors","role_family":"Semiconductors","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":69000,"max_usd":141000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":29},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bitcoin","optional":false},{"name":"HPC","optional":false},{"name":"ANSYS","optional":true}],"status":"live","first_seen_at":"2026-09-08T01:39:03Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-11-01T19:41:38Z","board_verified":true,"closed_at":null,"days_open":54,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":54},"description":"About Bitdeer:\nBitdeer is a world-leading technology company for Bitcoin mining and AI cloud.\nBitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.\nHeadquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.\nWhat you'll do:\nOwn the WoW stack definition and the TSV / hybrid-bond (HB) interface - partition, bond-pad pitch/array, keep-outs, and alignment budgets - co-defined with the foundry and the memory partner.\nDrive the 3D-aware floorplan inputs: bump/TSV/HB maps, micro-bump and ballmap planning, and die-to-die interface placement, in partnership with Physical Design.\nDefine and close DFM and 3D design rules; run design-rule and process-assumption reviews.\nCoordinate thermal and thermal-mechanical (stress / warpage) analysis, and feed mitigations back into floorplan, power delivery, and stack choices.\nDrive 3D signoff: thermal, SI/PI across the die-to-die interface, and known-good-stack assumptions - clean before tapeout.\nWork with DFT on the 3D test strategy (stacked-die test access, IEEE 1838 / known-good-die & known-good-stack) so the integration is testable.\nManage package / substrate co-design handoff to the OSAT (outsourced): stackup, escape, assembly flow, and yield/reliability considerations.\nTrack foundry and memory-partnerdeliverables and milestones, surface integration risks early, and keep the stack plan aligned with the schedule\nRequired qualifications:\nBS/MS/PhD in EE, Materials, Mechanical Engineering, or a related field.\n5+ years in 3DIC / advanced-packaging / process integration, with at least one product taken to tapeout and through assembly.\nDirect, hands-on experience with TSV and hybrid bonding and a 3D stacking flow (wafer-on-wafer, chip-on-wafer, or SoIC/CoWoS-class).\nWorking knowledge of TSMC 3DFabric (SoIC / CoWoS / InFO) or an equivalent foundry 3D ecosystem, including the associated design kits and rule decks.\nSolid grasp of thermal / thermal-mechanical behavior in stacked die and of SI/PI at the die-to-die interface.\nComfortable owningcross-organization interfaces - foundry, memory IP partner, and OSAT - and translating their constraints into actionable design inputs\nPreferred qualifications:\nExperience with DRAM-on-logic stacks, HBM-class memory integration, or high-bandwidth memory interfaces.\nBackground on AI / HPC accelerators or other high-power, high-bandwidth SoCs.\nFamiliarity with thermal/mechanical tools (e.g., Ansys) and 3D physical/signoff flows (Synopsys / Cadence).\nExposure to stacked-die test and yielddebug.\n\nExperience standing up a 3D-integration methodology on a small team - comfortable being the first/only specialist in the room.\nWhy this role:\nYou own a genuinely hard, defining problem on the chip - not a slice of someone else's flow.\nDirect line to the foundry and memory partner; your decisions set the stack.\nEarly-team seniority with room to shape the 3D methodology and grow the function.\nWhat you will experience working with us:\nA culture that values authenticity and diversity of thoughts and backgrounds;\nAn inclusive and respectable environment with open workspaces and exciting start-up spirit;\nFast-growing company with the chance to network with industrial pioneers and enthusiasts;\nAbility to contribute directly and make an impact on the future of the digital asset industry;\nInvolvement in new projects, developing processes/systems;\nPersonal accountability, autonomy, fast growth, and learning opportunities;\nAttractive welfare benefits and developmental opportunities such as training and mentoring.\n--------------------------------------------------------------------\nBitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. 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