{"id":1460761,"url":"https://alion.io/job/bitsilica-design-verification-manager-socasic","title":"Design Verification Manager - SoC/ASIC","company":{"id":3808085,"name":"Bitsilica","domain":"bitsilica.com","url":"https://alion.io/company/bitsilica","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":48000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-29T10:42:08Z","employer_posted_date":null,"last_verified_at":"2026-09-29T10:42:08Z","board_verified":false,"closed_at":null,"days_open":23,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":23},"description":"Position Summary :\n\nWe are seeking an experienced and results-driven Design Verification Manager to lead verification activities for complex IP, subsystem, SoC, and ASIC designs. \n\nThe ideal candidate will possess strong technical expertise in SystemVerilog/UVM-based verification methodologies, SoC integration, AMBA protocols, and team leadership.\n\nKey Responsibilities :\n\n- Lead and manage Design Verification teams for IP, subsystem, and SoC/ASIC verification projects.\n\n- Define verification methodologies, strategies, test plans, coverage goals, and execution timelines.\n\n- Drive development of scalable and reusable SystemVerilog/UVM-based verification environments.\n\n- Oversee verification of subsystem interfaces, Register Abstraction Layer (RAL), memory subsystems, and protocol compliance.\n\n- Guide teams in developing constrained-random, assertion-based, and coverage-driven verification environments.\n\n- Ensure successful verification closure including functional coverage, code coverage, assertions, regressions, and debug.\n\n- Manage project schedules, resource allocation, priorities, and risk mitigation across multiple concurrent programs.\n\nEducation & Experience :\n\n- BE/BTech/ME/MTech in Computer Science, Electronics, Electrical Engineering, or related field.\n\n- 6 - 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