{"id":1456397,"url":"https://alion.io/job/bitsilica-senior-staff-engineer-dft","title":"Senior Staff Engineer - DFT","company":{"id":3808085,"name":"Bitsilica","domain":"bitsilica.com","url":"https://alion.io/company/bitsilica","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":50000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1251},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys DFTMAX","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-09-29T08:34:46Z","employer_posted_date":null,"last_verified_at":"2026-09-29T08:34:46Z","board_verified":false,"closed_at":null,"days_open":11,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":11},"description":"Job Description : \n\nWe are looking for a highly experienced Lead / Principal DFT Engineer with 10+ years of hands-on expertise in Design-for-Testability (DFT) architecture, implementation, and verification. In this role, you will lead end-to-end DFT strategies across high-complexity cores and SoCs.\n\n You will be responsible for defining scan architectures, implementing advanced compression techniques, driving MBIST integration, and executing pattern generation, timing/non-timing simulations, and fault coverage optimization.\n\nKey Responsibilities : \n\nDFT Architecture & Implementation : \n\n- Architecture & Planning : Define and architect comprehensive DFT strategies at both the core and full SoC levels for multi-million gate designs.\n\n- Scan & Compression : Drive scan insertion, boundary scan, and advanced scan compression architectures (e.g., EDP, EDT) to minimize test time and silicon test cost.\n\n- Advanced Architectures : Implement and optimize Streaming Scan Network (SSN) architectures to improve packetized test data transport efficiency across complex SoCs.\n\n- Clocking & OCC : Design and integrate On-Chip Clock (OCC) logic for at-speed test, working closely with clock architecture teams to handle internal, functional, and test clock domains safely.\n\nMemory-BIST (MBIST) & Analog Integration : \n\n- Architect, insert, and verify Memory-BIST (MBIST) logic across various memory arrays (SRAM, ROM, multi-port memories), including repair and diagnostic features.\n\n- Integrate IEEE 1149.1 / 1149.6 (Boundary Scan) and IEEE 1687 (IJTAG) infrastructure.\n\nATPG & Coverage Optimization : \n\n- Lead ATPG pattern generation for Stuck-At, At-Speed (Transition Delay), Path Delay, and Cell-Aware fault models.\n\n- Conduct in-depth fault coverage analysis, identify coverage gaps, and implement testability enhancements (e.g., test point insertion) to meet target DPM (Defects Per Million) goals.\n\nVerification & Simulation : \n\n- Execute and debug timing (SDF annotated) and non-timing gate-level simulations (GLS) for all test modes (Scan, MBIST, Boundary Scan, At-Speed).\n\n- Resolve timing violations, race conditions, and X-bounding issues in test modes.\n\nCross-Functional Collaboration & Handoff : \n\n- Work closely with Physical Design, Synthesis, STA, and Analog IP teams to ensure clean DFT timing closure and minimal area/power overhead.\n\n- Deliver complete ATPG pattern packages (WGL, STIL) to ATE/Product Engineering teams and assist with silicon bring-up and pattern debug on automated test equipment.\n\nRequired Skills & Qualifications : \n\n- Experience : 10+ years of dedicated DFT experience on complex, multi-million gate SoCs in deep sub-micron technology nodes (7nm, 5nm, 3nm, or similar).\n\n- Scan & ATPG Expertise : Extensive hands-on experience in scan insertion, compression methodologies, pattern generation, and coverage debugging.\n\n- Tool Mastery : Hands-on experience with industry-standard EDA tools (e.g., Siemens EDA Tessent tool suite, Synopsys DFTMAX / Tetramax, or Cadence Modus).\n\n- Architecture Knowledge : Strong understanding of SSN (Streaming Scan Network) architecture, Clocking architectures/OCC, and Memory-BIST (MBIST) insertion.\n\n- Simulation Skills : Proven expertise in running, debugging, and resolving failures in both non-timing and SDF-annotated timing simulations (GLS).\n\n- Scripting : Proficiency in Tcl, Perl, or Python for test automation and tool flows.\n\n- Communication : Excellent verbal and written communication skills to collaborate across global cross-functional teams.\n\nPreferred Qualifications : \n\n- Prior experience leading DFT technical initiatives or mentoring junior DFT engineers.\n\n- Direct exposure to post-silicon bring-up, silicon debugging, and ATE pattern handoff/troubleshooting.\n\n- Knowledge of Automotive Safety (ISO 26262) DFT/BIST standards or Functional Safety requirements is a plus.\nSkills\nDFT, ATPG, MBIST, SoC, Verification, UE Simulator, Perl, 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