{"id":1503000,"url":"https://alion.io/job/blacksesame-asic-design-engineer","title":"ASIC Design Engineer","company":{"id":39462,"name":"Blacksesame","domain":"blacksesame.com","url":"https://alion.io/company/blacksesame","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":6000,"max":9000,"currency":"SGD","period":"month","gross":true,"usd_annual":84504},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Computer Vision","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-30T00:00:00Z","employer_posted_date":null,"last_verified_at":"2026-09-30T00:00:00Z","board_verified":false,"closed_at":null,"days_open":4,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":4},"description":"Company Overview\nBlack Sesame Technologies is a leading automotive-grade computing SoC and intelligent vehicle solution provider. Founded in 2016 and listed on the Hong Kong Stock Exchange, we innovate SoCs for autonomous driving and smart vehicle applications, empowering safer, smarter mobility.\nJob Summary\nAssist in designing micro-architecture and RTL for ISP and computer vision algorithms, supporting power, performance, and area analysis, and collaborating with cross-functional teams to ensure verification and validation of ASIC designs.\nResponsibilities\nDesign micro-architecture components for image signal processing (ISP) and computer vision (CV) algorithms to support intelligent vehicle solutions\nDevelop RTL code using Verilog/SystemVerilog and high-level synthesis (HLS) tools such as Catapult to implement ASIC designs\nAnalyze power, performance, and area metrics to optimize design efficiency and meet project requirements\nCollaborate with architects and design verification engineers to ensure thorough verification and successful signoff of designs\nPerform FPGA-related tasks including emulation, validation, and debugging to support hardware verification and prototype testing\nPreferred competencies and qualifications\nMaster’s degree or higher in Electrical, Electronics, or Computer Engineering\nExperience or project work related to ASIC design or image signal processing\nKnowledge of C/C++ programming for algorithm implementation and testing\nFamiliarity with ASIC design processes and frontend design methodologies\nUnderstanding of image, vision, or video data processing and algorithm acceleration techniques\nExperience with scripting languages such as Python, Perl, or Tcl to automate tasks and support design workflows\nStrong teamwork and communication skills to collaborate effectively in cross-functional teams\nAnalytical mindset with a willingness to learn and adapt in a dynamic engineering environment\nSkills\nPerl, Analytical Skills, Architect, Scripting, Soft Skills, RTL Design, Python, Debugging, Verilog, Mechanical Engineering","description_format":"text","description_chars":2066,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Autonomous Driving","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-30T04:00:44Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":21,"reasons":["seen:3","velocity","win:early"],"computed_at":"2026-10-03T05:45:00Z"},"pay":{"stated_usd_annual":84504,"is_top_pay":false},"html_url":"https://alion.io/job/blacksesame-asic-design-engineer","json_url":"https://alion.io/job/blacksesame-asic-design-engineer.json","meta":{"generated_at":"2026-10-04T01:54:06Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2566,"day_limit":5000,"remaining_today":2434,"minute_limit":60,"resets_at":"2026-10-05T00:00:00Z"}}}