Senior/Physical Design Engineer

Position Overview

We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.

Responsibilities

• Manage the entire physical design process, including RTL to GDS implementation, for complex semiconductor chips.
• Achieve block-level timing closure by optimizing design constraints, performing timing analysis, and applying optimization techniques.
• Conduct formal checks to ensure the design adheres to functional and timing requirements.
• Perform low power checks and analyze power consumption to optimize power efficiency.
• Collaborate with the design team to develop and implement UPF (Unified Power Format) for power management and control.
• Conduct block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), Formal Verification (FM), and Voltage-Current-Latency-Power (VCLP) signoff.
• Utilize Synopsys and Cadence ARP (Automated Routing and Place) tools to achieve high-quality physical design.
• Develop and utilize scripts in Tcl, Perl, or Python to automate design tasks and enhance the design flow.
• Apply your expertise in automotive chip physical design to meet the specific requirements and standards of automotive applications.

Qualification/ Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 3 years of hands-on experience in physical design, working on complex semiconductor chips.
• Strong experience and understanding of advanced process nodes such as 7nm, 6nm, or 5nm.
• Proficiency in low power design techniques and hands-on experience with UPF.
• Experience with block-level APR, STA, PI, PV, FM, and VCLP, using industry-standard tools.
• Proficient with Synopsys and Cadence ARP tools for physical design.
• Familiarity with scripting languages such as Tcl, Perl, or Python for automation and design flow improvement.
• Knowledge and experience in automotive chip physical design, including compliance with automotive standards and requirements.

Skills

Perl, Timing Closure, GDS, TCL, Synopsys tools, Power Quality Management, Script Development, Python, Cadence, RTL Synthesis, Physical Design