{"id":193272,"url":"https://alion.io/job/blueorigin-asic-engineering-director","title":"ASIC Engineering Director","company":{"id":3698,"name":"Blue Origin","domain":"blueorigin.com","url":"https://alion.io/company/blueorigin","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":92,"open_postings":262,"ghost_share":0,"stale_share":0.321,"repost_share":0.004,"time_to_fill_p50_days":43,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"head","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Kraków, Poland"],"countries":["PL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":124000,"max_usd":237000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":82},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Cadence Virtuoso","optional":true}],"status":"live","first_seen_at":"2026-09-02T00:00:00Z","employer_posted_date":"2026-09-02","last_verified_at":"2026-10-22T03:59:12Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"Application close date:\nApplications will be accepted on an ongoing basis until the requisition is closed.At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!\nBlue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.Blue Origin is seeking an experienced ASIC Engineering Director & Site Leader to establish and lead the ASIC engineering organization in Krakow, Poland. The Krakow team will have a strong emphasis on design verification, while also developing capabilities in front-end design, digital architecture and implementation, embedded hardware integration, and selected digital-top mixed-signal functions. The Krakow organization will contribute to the development of complex communication systems and high-performance SoCs for TeraWave supporting Blue Origin’s mission of enabling millions of people to live and work in space for the benefit of Earth. The successful candidate will combine deep technical expertise in ASIC and communication SoC development with demonstrated experience building high-performing teams, establishing effective engineering processes, and delivering complex silicon products. In addition to leading the ASIC organization, this person will serve as the Krakow engineering site leader and will have responsibility for the site’s shared ASIC and prototype integration laboratory. Lab execution will be supported through technical leads in design verification, software, firmware, and RF/mixed-signal engineering. The lab will support FPGA prototyping, hardware-in-the-loop testing, embedded software and firmware integration, modem and digital beamformer development, and system-level debug. This role will partner closely with ASIC, systems, software, firmware, analog/mixed-signal, RF, physical design, DFT, product engineering, and program leadership teams across Blue Origin. While this position is not expected to directly manage the analog/mixed-signal organization, prior experience with communication SoCs and digital-top mixed-signal design, integration, and verification will be highly valuable.\nResponsibilities:\nEstablish, lead, and grow the Krakow ASIC engineering organization, initially with a strong focus on design verification and expanding into front-end design, digital architecture, and related digital functions.\nDefine and execute the organization’s technical strategy, staffing plan, operating model, engineering processes, and development roadmap.\nRecruit, develop, mentor, and retain engineering managers, technical leads, staff engineers, and individual contributors.\nBuild a culture of technical excellence, ownership, collaboration, accountability, and continuous improvement.\nLead ASIC development across the product lifecycle, from requirements and architecture through RTL design, verification, implementation, tape-out, silicon bring-up, and product qualification.\nOwn the Krakow team’s execution against program commitments, including scope, schedule, quality, staffing, resource planning, and risk management.\nEstablish scalable ASIC verification methodologies and infrastructure for block-, subsystem-, and SoC-level verification.\nEnsure disciplined verification planning and closure, including requirements traceability, test planning, functional and code coverage, assertions, formal verification, emulation, FPGA prototyping, gate-level simulation, software simulation, and regression management.\nBuild strong collaboration between design and verification teams to improve design quality, reduce integration risk, and accelerate issue discovery and closure.\nSupport the development of digital front-end capabilities, including RTL design, microarchitecture, CDC/RDC, lint, clocking, low-power and multi-voltage design, interface integration, and design quality.\nProvide technical oversight for integration of complex digital and communication SoCs, including processors, bus fabrics, DMA, NoCs, memory controllers, highspeed interfaces, external IP, and analog/mixed-signal macros.\nGuide development and verification of DSP-intensive communication systems, including modem architectures, coding and framing, PHY and MAC functions, FIR filters, CORDIC, FFT/IFFT, MAC engines, circular buffers, and time-bound data movement.\nPromote the use of golden reference models and cross-domain verification using MATLAB, System C, C/C++, Python, and System Verilog.\nEnsure robust verification of digital-top mixed-signal systems through appropriate behavioral models, co-simulation, analog macro abstraction, and system-level validation.\nPartner with analog/mixed-signal and RF leaders to establish effective specifications, interfaces, models, integration plans, and verification strategies.\nSupport implementation, DFT, LEC, floorplanning, static timing analysis, power analysis, physical verification, and signoff activities.\nEstablish effective flows between ASIC and FPGA implementations, emulation, prototyping, pre-silicon verification, and post-silicon validation.\nPartner with software and firmware teams on hardware/software co-simulation, processor integration, boot flows, drivers, diagnostics, and system-level validation.\nParticipate in silicon bring-up, characterization, failure analysis, root-cause investigation, and corrective action following tape-out.\nLead technical reviews, architecture assessments, design reviews, verification reviews, and lessons-learned activities.\nServe as the accountable engineering leader for the Krakow ASIC and prototype integration lab, with execution delegated through technical leads for design verification, software, firmware, and RF/mixed-signal engineering.\nEnsure that shared lab infrastructure effectively supports FPGA prototyping, hardware-in-the-loop testing, embedded software and firmware integration, modem and digital beamformer development, and system-level debug.\nEstablish appropriate processes for lab planning, equipment configuration, prototype tracking, test automation, data management, maintenance, calibration, safety, and infrastructure reliability.\nPartner with facilities, IT, security, procurement, and EHS teams on lab operations, equipment procurement, physical infrastructure, access controls, and safe operation.\nManage lab capacity and capital planning in alignment with program priorities and organizational growth.\nDevelop strong working relationships with engineering leaders and stakeholders in Krakow and across Blue Origin’s global organization.\nRepresent the Krakow ASIC organization in program reviews, planning activities, technical forums, and executive discussions.\nEstablish a collaborative, inclusive, and high-performing Krakow engineering site culture in partnership with other functional leaders.\nSupport local site operations, workforce planning, employee development, engineering communications, and cross-functional coordination.\nTravel as required to support collaboration with other Blue Origin locations, suppliers, technology partners, and program teams.\nMinimum Qualifications:\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.\n15+ years of relevant experience in ASIC, SoC, semiconductor, or complex digital system development.\n8+ years of experience leading engineering organizations, including responsibility for hiring, team development, execution, and technical direction.\nDemonstrated experience leading the development and delivery of complex ASICs or SoCs through tape-out and silicon bring-up.\nSignificant experience with design verification of complex SoCs using System Verilog and modern verification methodologies.\nStrong understanding of verification planning and closure, including functional coverage, code coverage, assertions, formal verification, regressions, emulation, FPGA prototyping, gate-level simulation, and software co-simulation.\nExperience leading teams responsible for block-, subsystem-, and full-SoC verification.\nStrong understanding of digital front-end design and ASIC implementation flows, including RTL design, CDC/RDC, lint, timing constraints, clocking, low-power or multi-voltage design, DFT, LEC, floorplanning, static timing analysis, and power analysis.\nExperience integrating complex SoC components, such as processors, cache and memory subsystems, MMUs, interrupt controllers, secure boot, bus fabrics, AXI, DMA, NoCs, and external IP.\nExperience with high-speed and system interfaces such as DDR, PCIe, Ethernet, SPI, and high-speed SerDes.\nExperience with DSP-intensive systems and/or modern communication SoCs, including modem, PHY, MAC, coding, framing, and high-throughput data movement.\nDemonstrated ability to define requirements, specifications, development plans, verification plans, schedules, and technical milestones.\nExperience building or operating a hardware, ASIC, FPGA, embedded systems, RF, or system-integration laboratory.\nExperience with hardware-in-the-loop testing, FPGA prototyping, lab automation, or automated hardware regression infrastructure.\nDemonstrated ability to lead through functional technical leads across multiple engineering disciplines.\nStrong technical judgment and the ability to balance performance, power, area, schedule, quality, cost, and risk.\nExcellent written, verbal, and interpersonal communication skills.\nDemonstrated ability to lead through influence across geographically distributed and cross-functional teams.\nAbility to work onsite in Krakow, Poland.\nPreferred Qualifications:\nMS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.\nExperience building a new ASIC or semiconductor engineering organization or establishing a new engineering site.\nExperience leading organizations spanning design verification, RTL/front-end design, digital architecture, emulation, FPGA prototyping, and post-silicon validation.\nDeep experience with communication SoCs, modem architectures, wireless or satellite communications, RF systems, or other DSP-intensive products.\nExperience with DSP architectures including FIR, CORDIC, FFT/IFFT, MAC, channelization, sample-rate conversion, circular buffers, and analog-to-digital interfaces.\nExperience with deterministic latency, time-slotted systems, timestamping, and real-time data processing.\nExperience developing reusable verification environments and portable verification flows across simulation, emulation, FPGA, pre-silicon, and silicon environments.\nExperience integrating software build flows with simulation, FPGA, emulation, and verification environments.\nExperience qualifying FPGA prototypes or emulation platforms and partitioning verification across simulation, emulation, and prototyping.\nExperience with digital-top mixed-signal SoCs, including analog macro modeling, AMS co-simulation, mixed-mode verification, and top-level integration.\nFamiliarity with analog/mixed-signal design and verification flows and tools such as Cadence Virtuoso, Spectre, AMS, MATLAB, and SystemVerilog-AMS.\nExperience collaborating with analog, RF, PLL, data converter, power management, and other mixed-signal design teams.\nExperience with silicon characterization, post-silicon debug, production test, and yield improvement.\nExperience managing external IP vendors, design partners, EDA providers, foundries, and technology partners.\nExperience establishing shared engineering lab processes, including equipment procurement, asse...","description_format":"text","description_chars":13177,"description_truncated":true,"requirements":{"experience_years_min":15,"management_years_min":8,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[{"language":"Polish","level":"Advanced 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