{"id":656388,"url":"https://alion.io/job/bolt-lead-vector-compute-architect","title":"Lead Vector Compute Architect","company":{"id":668900,"name":"Bolt Graphics","domain":"bolt.graphics","url":"https://alion.io/company/bolt-6","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":91,"open_postings":28,"ghost_share":0.071,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":75,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":250000,"max":350000,"currency":"USD","period":"year","gross":null,"usd_annual":350000},"salary_estimate":null,"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"C++","optional":false},{"name":"HPC","optional":false},{"name":"SystemC","optional":false}],"status":"live","first_seen_at":"2026-05-27T02:55:37Z","employer_posted_date":"2026-05-27","last_verified_at":"2026-10-17T13:27:12Z","board_verified":true,"closed_at":null,"days_open":143,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":143},"description":"Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.\nOur Values\nBe Fearless: Unmute yourself. Test boundaries and get proven right.\nRemain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.\nEducate Your Ego: Selflessly collaborate towards our shared purpose.\n About the role:\nWe are looking for an experienced and highly motivatedLeadVector ComputeArchitect to lead the architecture definition and technical direction forBolt’snext-generationGPUs. The ideal candidate will have strongexpertiseindataparallelcomputeunitarchitecture development, performance modeling,data pathintegration, and cross-functional collaboration across hardware, software, and systemsteams.\nThis role involves defining scalable and high-performance architectures for advancedcomputeworkloadsincludinggraphics,HPC,andsystem management.This role is on-site and requires someone to be local to the Bay Area.\nWhat you'll do:\nDefine data parallel microarchitecture satisfying ISA constraints. \nDrive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability. \nDevelop and review system architecture specifications, interface definitions, and microarchitecture requirements. \nCollaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle. \nLead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC or similar modeling environments. \nDefine memory hierarchy, coherency architecture, and cache structures. \nWork closely with verification teams to define architectural test plans and validation strategies. \nSupport silicon bring-up, debug, performance tuning, and post-silicon optimization. \nContribute to long-term technology and product roadmap planning. \nQualifications:\nStrong understanding of modern data parallel microarchitectures and subsystem integration. \nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. \n6+ years of experience in modern data parallel microarchitecture including: \nWorkload characterization and profiling \nPerformance modeling \nOut-of-order data dependency and control \nUtilization / occupancy optimization \nHigh-performance architecture design techniques\nExperience with one or more of the following:\nCPU/GPU/NPU architectures \nNoC/interconnect architectures \nCache coherency protocols (CHI/ACE/CXL) \nHigh-speed interfaces (PCIe, UCIe, Ethernet) \nMemory systems (DDR, LPDDR, HBM, GDDR) \nPower,performance,andareaoptimization \nStrong knowledge of RTL development and verification methodologies. \nExperience with architecture modeling and performance analysis tools. \nFamiliarity with firmware/software interaction in complex SoC systems. \nExcellent problem-solving, communication, and leadership skills. \nCompensation Range: $250,000-$350,000per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.\nBenefits:\nMedical, Dental, & Vision - 100% covered premiums\nEquity - Stock Options\n401(k) match\nWFH Hardware\nBolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. 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