{"id":656395,"url":"https://alion.io/job/bolt-rtl-design-microarchitecture-engineer","title":"RTL Design / Microarchitecture Engineer","company":{"id":668900,"name":"Bolt Graphics","domain":"bolt.graphics","url":"https://alion.io/company/bolt-6","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":91,"open_postings":28,"ghost_share":0.071,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":75,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":160000,"max":220000,"currency":"USD","period":"year","gross":null,"usd_annual":220000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-04-16T21:42:54Z","employer_posted_date":"2026-04-16","last_verified_at":"2026-10-17T13:27:12Z","board_verified":true,"closed_at":null,"days_open":183,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":183},"description":"Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.\nOur Values\nBe Fearless: Unmute yourself. Test boundaries and get proven right.\nRemain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.\nEducate Your Ego: Selflessly collaborate towards our shared purpose.\n About the role:\nAs anRTL Design / Microarchitecture Engineer, you will define and implement key microarchitectural components of our SoC/IP. You will work closely with architecture, verification, and physical design teams to deliver high-performance, scalable, and power-efficient designs. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available.\nWhat you'll do:\nDefine and develop microarchitecture specifications from high-level architecture requirements\nDesign and implement RTL (SystemVerilog/Verilog) for complex digital blocks\nDrive performance, power, and area (PPA) optimizations at the RTL and microarchitecture level\nCollaborate with verification teams to ensure high coverage and design correctness\nSupport integration of IPs into SoC-level environments\nWork with physical design teams for timing closure, synthesis constraints, and floorplan-aware design\nDebug and resolve issues during simulation, GLS, and silicon bring-up\nParticipate in design reviews, architecture discussions, and cross-functional planning\nContribute to design documentation and methodology improvements\nRequired Qualifications:\nBachelor’s/Master’s degree in Electrical Engineering or related field\n5-10 years of experience in RTL design and microarchitecture\nStrong expertise in:\nRTL design using SystemVerilog/Verilog\nMicroarchitecture development for complex digital systems\nPerformance optimization and pipelining techniques\n\nExperience with simulation and debugging tools such as:\nSynopsys VCS / Cadence Xcelium\n\nFamiliarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler)\nStrong understanding of digital design fundamentals (FSMs, pipelines, caches, memory interfaces)\nExperience working in ASIC/SoC development environments\nPreferred Qualifications:\nExperience in one or more domains:\nCPU, GPU, AI/ML accelerators, networking, or high-speed data processing\n\nKnowledge of memory subsystem design (SRAM, cache hierarchies, coherency)\nFamiliarity with low-power design techniques (clock gating, power domains)\nExposure to formal verification or linting tools\nExperience with GLS, SDF annotation, and silicon debug\nScripting skills (Python/TCL) for automation\nUnderstanding of hardware-software interaction (firmware, drivers)\nCompensation Range: $160,000-$220,000per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.\nBenefits:\nMedical, Dental, & Vision - 100% covered premiums\nEquity - Stock Options\n401(k) match\nWFH Hardware\nBolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. 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