{"id":656410,"url":"https://alion.io/job/bolt-staff-senior-staff-physical-design-engineer","title":"Staff / Senior Staff Physical Design Engineer","company":{"id":668900,"name":"Bolt Graphics","domain":"bolt.graphics","url":"https://alion.io/company/bolt-6","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":91,"open_postings":33,"ghost_share":0.061,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":75,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":200000,"max":220000,"currency":"USD","period":"year","gross":null,"usd_annual":220000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Ansys RedHawk","optional":true}],"status":"live","first_seen_at":"2026-04-17T00:10:03Z","employer_posted_date":"2026-04-17","last_verified_at":"2026-11-01T02:58:16Z","board_verified":true,"closed_at":null,"days_open":198,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":197},"description":"Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.\nOur Values\nBe Fearless: Unmute yourself. Test boundaries and get proven right.\nRemain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.\nEducate Your Ego: Selflessly collaborate towards our shared purpose.\n About the role:\nAs a Staff / Senior Staff Physical Design Engineer, you will be responsible for driving full-chip or block-level physical implementation from netlist to GDSII. You will play a critical role in achieving timing, power, and area (PPA) targets while ensuring high-quality tapeouts. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available.\nWhat you'll do:\nOwn end-to-end physical design flow: synthesis support, floorplanning, placement, CTS, routing, and signoff\nDrive timing closure (setup/hold) across multiple PVT corners using advanced STA methodologies (OCV/POCV)\nPerform and debug DRC/LVS/EM/IR issues and drive clean signoff\nWork closely with RTL, architecture, and verification teams for design convergence\nHandle ECO flows, including late-stage timing and functional fixes\nOptimize designs for power, performance, and area (PPA)\nIntegrate and validate hard macros (SRAMs, IOs, analog blocks)\nSupport GLS, SDF generation, and debug timing-related issues\nDevelop and enhance automation scripts (TCL/Python) for PD flows\nCollaborate with foundry/vendor teams during tapeout and signoff\nRequired Qualifications:\nBachelor’s/Master’s degree in Electrical Engineering or related field\n8-12 years of experience in ASIC physical design\nProven experience in full-chip or large block implementation and tapeouts\nStrong expertise in:\nFloorplanning and power planning\nPlacement, CTS, routing, and physical verification\nStatic Timing Analysis (STA) and timing closure\n\nHands-on experience with industry-standard tools such as:\nSynopsys ICC2 / Cadence Innovus\nSynopsys PrimeTime\nMentor Calibre\n\nExperience with advanced nodes (7nm and below preferred)\nStrong debugging and problem-solving skills\nPreferred Qualifications:\nExperience with low-power design techniques (UPF/CPF)\nKnowledge of EMIR analysis (e.g., Ansys RedHawk-SC)\nFamiliarity with multi-voltage designs and power domains\nExperience with high-speed interfaces or complex SoCs (CPU/GPU/AI)\nExposure to GLS and timing-related silicon debug\nScripting expertise in Python/TCL\nCompensation Range: $200,000-$220,000per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.\nBenefits:\nMedical, Dental, & Vision - 100% covered premiums\nEquity - Stock Options\n401(k) match\nWFH Hardware\nBolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. 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