{"id":1285557,"url":"https://alion.io/job/brace-infotech-dft-engineer","title":"DFT Engineer","company":{"id":3801238,"name":"Brace Infotech","domain":"braceinfotech.com","url":"https://alion.io/company/brace-infotech","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":16500,"max_usd":34000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":9},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Tessent","optional":false},{"name":"Cadence Allegro","optional":true},{"name":"Cadence Xcelium","optional":true}],"status":"live","first_seen_at":"2026-08-13T12:04:55Z","employer_posted_date":null,"last_verified_at":"2026-08-13T12:04:55Z","board_verified":false,"closed_at":null,"days_open":48,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":48},"description":"Role : \n\nThe candidate is expected to have clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.\n\nRequirements : \n\n- Should have experience in at least one : MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.\n\n- Good to have worked on zero delay as well as SDF Timing Simulations.\n\n- Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.\n\n- Good to have worked on fault models like stuck-at, Transition Delay Faults (TDF), IDDQ and should have experience in scan test coverage improvement techniques.\n\n- Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and/or production activities with exposure to Tester debug using shmoo plots and graphs.\n\n- The candidate should have experience of providing test mode timing constraints to STA and PD teams.\n\n- Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.\n\nSkills\nDFT, MBIST, ATPG, Synopsys, Cadence Allegro","description_format":"text","description_chars":1357,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Professional Services","Human Resources","Recruiting & Staffing"],"lifecycle":[{"event":"open","at":"2026-09-26T04:00:00Z"}],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":0.4,"p_active":0.455,"p_room":0.35,"age_days":48,"expected_fill_days":18,"reasons":["seen:48","velocity","win:tail"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/brace-infotech-dft-engineer","json_url":"https://alion.io/job/brace-infotech-dft-engineer.json","meta":{"generated_at":"2026-10-01T10:54:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2127,"day_limit":5000,"remaining_today":2873,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}