{"id":1157685,"url":"https://alion.io/job/broadcom-asic-chip-lead","title":"ASIC Chip Lead","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":87,"open_postings":101,"ghost_share":0,"stale_share":0.525,"repost_share":0,"time_to_fill_p50_days":27,"computed_at":"2026-09-24T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States","Irvine, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":143800,"max":230000,"currency":"USD","period":"year","gross":null,"usd_annual":230000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Verilog","optional":false},{"name":"C++","optional":true},{"name":"MATLAB","optional":true},{"name":"Perl","optional":true},{"name":"Simulink","optional":true}],"status":"live","first_seen_at":"2026-09-23T22:15:58Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-09-24T21:54:03Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nBroadcom is seeking a highly experienced and accomplished Principal ASIC Chip Lead to lead the development of cutting-edge System-on-Chip (SoC) solutions. This key role requires a deep, end-to-end understanding of the entire ASIC architecture, design, and verification flow-from initial concept and RTL development through GDSII tape-out and into mass production.\nResponsibilities:\nManage cross-functional project teams while interfacing directly with a tier-1 customer. Must have soft skills to manage and diffuse high stakes.\nWork with architecture team to define micro-architecture for various design blocks & subsequently Verilog RTL development\nRun various frontend tools to check for linting, clock domain crossing, Low Power design, and checks using UPF/CPF flow\nWork with verification team to collaborate on test plan, coverage plan, and coverage closure\nWork with physical design team on design constraints and timing closure\nWork with firmware and systems team and help with bring-up on FPGA and Silicon platforms\nWork with operations team to bring silicon into mass production\nWilling to learn new areas and flexible in taking on any of the above tasks to help meet project goals\nRequired Qualifications:\nBSEE with 12+ YEARS of experience or MSEE with 10+ YEARS experience in Microarchitecture & RTL Design\nDetailed understanding of RTL design, logic synthesis, static timing analysis, design verification, clock domain crossing, and low power design techniques\nStrong Logic Design & RTL Design Skills using Verilog HDL\nExcellent written and verbal communication skills\nAbility to understand engineering and microarchitecture specifications\nKnowledge and experience of ARM-based SoC, DSP-based design, understanding of analog interfaces and designs is a definite advantage\nExperience with peripherals such as I2C, SPI, SPMI, UART, Asynchronous interface designs, Digital Signal Processing, Memory Controllers, peripherals, and interconnect protocols such as AHB, AXI, etc.\nExperience with Low Power Design & design verification techniques, Multiple Power domains, UPF/CPF understanding and usage\nGood knowledge of EDA tools\nWillingness to work on any design tools/flow/methodologies, including Design-Verification as needed during project development and not strictly limited to RTL design work\nDesired Skills:\nSolid understanding of communication basics\nExperience with implementation of arithmetic hardware (fixed point, floating point, transcendental operations)\nFamiliar with signal processing and numerical analysis tools like MATLAB\nExperience and understanding of DSP Designs using MATLAB/Simulink is a definite advantage, but not limited to DSP designs\nAble to work in a lab with logic analyzers and oscilloscopes during Silicon/FPGA bring up\nExperience with C/C++ and Scripting languages (Perl/Tcl)\nExperience with utilizing AI tools\nCompensation and Benefits\nThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00\nAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.","description_format":"text","description_chars":4458,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-23T22:15:58Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":0,"expected_fill_days":27,"reasons":["conf:7","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-09-24T05:45:00Z"},"pay":{"stated_usd_annual":230000,"is_top_pay":true},"html_url":"https://alion.io/job/broadcom-asic-chip-lead","json_url":"https://alion.io/job/broadcom-asic-chip-lead.json","meta":{"generated_at":"2026-09-24T23:05:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1292,"day_limit":5000,"remaining_today":3708,"minute_limit":60,"resets_at":"2026-09-25T00:00:00Z"}}}