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If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nJob Description\nWhat You can Expect -\n- Work on Latest cutting edge CSG Switches.\n- To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem.\n- Develop and maintain verification Environment in Mix of SV/UVM.\n- Understanding of the End to End spec along with Network & System topology.\n- Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level.\n- Coverage Closures, Gate Level Simulations along with end to end verification cycle.\nWhat we are looking for -\n- Bachelor's/Masters/PhD with Verification experience of 8+ years\n- Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST\n- Exposure to any one of the scripting languages - Perl or Python or SED/Awk\n- Expertise in Co-Simulations (HW/SW) Flow and debugs\n- Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary.\n- Expertise in the High Speed bus protocols desired - PCIe, Ethernet, AXI4.0\n- Exposure the Chip level Interconnect/Testability Functions - JTAG, I2C, PLLs etc\n- Experience in GLS, Coverage Driven Methodology, ATE\n- Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper.\n- Exposure to Test Bench Accelerators /Emulation Platforms.\nBroadcom is proud to be an equal opportunity employer. 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