{"id":3492697,"url":"https://alion.io/job/broadcom-asic-verification-engineer-4","title":"ASIC Verification Engineer","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":66,"ghost_share":0.015,"stale_share":0.515,"repost_share":0.015,"time_to_fill_p50_days":35,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-29T00:00:00Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-11-02T12:47:43Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nJob Description:\nDevelop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features\nDevelop verification environments using System Verilog and UVM\nArchitect and develop scalable and re-usable test benches, using the framework of the verification methodology\nDevelop BFMs / Checkers / monitors / Scoreboards\nBuild pseudo-random tests to verify and get full Functional coverage\nDebug Regression failures in RTL and Gatelevel simulations, analyze Functional Coverage gaps and improve tests to cover the gaps\nDocument verification strategy including Test plans, Testbench, Random tests, etc.\nRequirements:\nBachelor’s or Master’s degree in electrical engineering or related degree with 8+ years relevant experience\nProficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM\nGood command of Object-Oriented Programming principles\nKnowledge of Host interface protocols such as PCIe, SAS, SATA is desired\nKnowledge of AMBA AXI/AHB/APB protocols\nExperience writing Functional Coverage, pseudo random tests\nFlexible to work in any IP/Subsystem/SoC projects\nCapability to work independently and deliver\nBroadcom is proud to be an equal opportunity employer. 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