{"id":454919,"url":"https://alion.io/job/broadcom-design-engineer-sta","title":"Design Engineer - STA","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":88,"open_postings":72,"ghost_share":0,"stale_share":0.486,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Fort Collins, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":109700,"max":175500,"currency":"USD","period":"year","gross":null,"usd_annual":175500},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Tempus","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Ruby","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"TCL Scripting","optional":false},{"name":"Unix","optional":false}],"status":"live","first_seen_at":"2026-09-01T00:00:00Z","employer_posted_date":"2026-09-01","last_verified_at":"2026-10-26T13:10:16Z","board_verified":true,"closed_at":null,"days_open":55,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":55},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nBe part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.\nRole Overview\nThis STA Engineering role focuses on chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes and involves working across multiple design hierarchies to define, validate, and sign off complex timing environments for AI, computing, and networking SoCs.\nKey Responsibilities\nDevelop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.\n\nPerform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or Cadence Tempus.\n\nDefine and execute timing signoff methodologies, including process corners, derates, and uncertainties.\n\nConduct pre- and post-route timing analysis, quality of results (QoR) evaluations, and closure verification.\n\nGenerate and validate timing ECOs to achieve signoff-quality closure across PVT corners.\n\nAutomate timing flows and analysis using Tcl and scripting languages such as Perl or Python.\n\nCollaborate with physical design, synthesis, and clock teams to ensure timing convergence and cross-domain consistency.\n\nAnalyze and debug timing violations, signal integrity issues, and clock network challenges.\n\nSupport power and performance optimization through informed timing analysis and constraint tuning.\n\nEnsure full compliance with timing signoff checklists, methodology, and documentation.\n\nTechnical Skills / Background\nDeep understanding of VLSI design principles and ASIC physical design fundamentals.\n\nWorking knowledge of PLLs, clock network design, and timing elements such as flip-flops, latches, and memories.\n\nProficiency in timing constraint creation, debugging, and validation.\n\nStrong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.\n\nFamiliar with setup/hold analysis, multi-mode multi-corner (MMMC) timing, and ECO convergence.\n\nExposure to advanced STA techniques, including POCV/SOCV/LVF, PBA, and SPICE correlation.\n\nKnowledge of timing libraries (CCS/ECSM/NLDM) and multi-input switching (MIS) effects.\n\nCoding & Tool Proficiency\nStrong experience with Tcl scripting and Linux/UNIX environments.\n\nProficiency in Python, Perl, or Ruby preferred.\n\nHands-on experience with Synopsys and/or Cadence STA tools highly desirable.\n\nCollaboration and Leadership\nExcellent communication, analytical, and problem-solving abilities.\n\nAbility to work effectively with external customers, cross-functional and global design teams.\n\nSkilled at organizing and presenting large data sets, prioritizing tasks, and driving to closure.\n\nDemonstrates independent decision-making and strong engineering judgment.\n\nProvides technical leadership, mentoring, and initiative in methodology improvements.\n\nEducation and Experience\nBSin Electrical or Computer Engineering with 8+ yearsof relevant experience, or\n\nMSin Electrical or Computer Engineering with 6+ yearsof relevant experience.\n\nCompensation and Benefits\nThe annual base salary range for this position is USD 109,700.00 To USD 175,500.00\nAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.","description_format":"text","description_chars":4990,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["RF & Wireless Hardware","Virtualization & Containers","Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-06T09:28:56Z"}],"visa":[],"liveness":{"score":24,"band":"cold","label":"Long shot","p_open":0.9,"p_active":0.753,"p_room":0.36,"age_days":55,"expected_fill_days":34,"reasons":["conf:66","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":{"stated_usd_annual":175500,"is_top_pay":true},"html_url":"https://alion.io/job/broadcom-design-engineer-sta","json_url":"https://alion.io/job/broadcom-design-engineer-sta.json","meta":{"generated_at":"2026-10-26T16:02:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":21383,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":95},"rest":"https://alion.io/mcp/rest/get_company?id=95"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fbroadcom-design-engineer-sta"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fbroadcom-design-engineer-sta"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fbroadcom-design-engineer-sta"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/broadcom-design-engineer-sta\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fbroadcom-design-engineer-sta"}]}