{"id":39112,"url":"https://alion.io/job/broadcom-design-verification-engineer","title":"Design Verification Engineer","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":88,"open_postings":78,"ghost_share":0,"stale_share":0.474,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Broomfield, United States","San Diego, United States","Fort Collins, United States","San Jose, United States","Irvine, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":143800,"max":230000,"currency":"USD","period":"year","gross":null,"usd_annual":230000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Cadence Palladium","optional":true},{"name":"Formal Verification","optional":true},{"name":"Siemens Veloce","optional":true},{"name":"Synopsys ZeBu","optional":true},{"name":"Tessent","optional":true}],"status":"live","first_seen_at":"2026-08-04T00:00:00Z","employer_posted_date":"2026-08-04","last_verified_at":"2026-10-19T22:13:11Z","board_verified":true,"closed_at":null,"days_open":77,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":77},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nDesign Verification Engineer\nBroadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments.\nThe engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.\nThe candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.\nRequirements:\n12+ years of experience with verification concepts and architectures for complex digital and MXS circuits\n\nExperience verifying designs at the block and system levels.\n\nExperience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)\n\nExperience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits\n\nExperience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)\n\nExperience with Synopsys, Cadence, and Mentor simulations tools\n\nDemonstrated ability to plan and deploy complex, reusable, and scalable verification environments\n\nExperience with Perl/Python and Tcl or other scripting languages\n\nExperience with version control systems (DesignSync, git)\n\nSuperior writing, grammar, and verbal communication skills\n\nExcellent problem solver; develops and employs automated processes where applicable\n\nWorked independently and in a global team and dynamic environment in a highly visible role\n\nPossesses ability to learn and adapt to new tools and methodologies on the fly\n\nMust have legal authorization to work in the US\n\nIt is a plus if the candidate has expertise in one or more of the following areas:\nExperience with hardware design and debug\n\nExperience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms\n\nFormal verification concepts / experience is a plus\n\nExperience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus\n\nExperience with co-simulation a plus\n\nEducation and Experience required:\nBS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.\n\nCompensation and Benefits\nThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00\nAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.","description_format":"text","description_chars":4833,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["RF & Wireless Hardware","Virtualization & Containers","Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-04T00:00:00Z"},{"event":"close","at":"2026-08-24T00:14:02Z"},{"event":"reopen","at":"2026-09-01T19:09:13Z"}],"visa":[],"liveness":{"score":19,"band":"cold","label":"Long shot","p_open":1,"p_active":0.676,"p_room":0.28,"age_days":77,"expected_fill_days":34,"reasons":["conf:7","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":{"stated_usd_annual":230000,"is_top_pay":false},"html_url":"https://alion.io/job/broadcom-design-verification-engineer","json_url":"https://alion.io/job/broadcom-design-verification-engineer.json","meta":{"generated_at":"2026-10-20T07:58:04Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8432,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":95},"rest":"https://alion.io/mcp/rest/get_company?id=95"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fbroadcom-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fbroadcom-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fbroadcom-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/broadcom-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fbroadcom-design-verification-engineer"}]}