{"id":3476735,"url":"https://alion.io/job/broadcom-dft-engineer-5","title":"DFT Engineer","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":63,"ghost_share":0.016,"stale_share":0.54,"repost_share":0.016,"time_to_fill_p50_days":35,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-10-28T00:00:00Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-11-06T19:39:58Z","board_verified":true,"closed_at":null,"days_open":9,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":9},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nAs a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.\nKey Responsibilities:\nWork closely with the ATE engineer on yield improvement and analysis.\nDevelop ATE patterns, manage the hand-off process, and perform silicon debugging.\nParticipate in block and chip-level DFT implementation, developing and executing all related tasks.\nWork on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.\nPerform ATPG and pattern simulation for both MBIST and scan.\nCollaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.\nEngage with various cross-functional team members, with opportunities to enhance our DFT design methodology.\nRequired Qualifications:\nBachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience\nRequired experience in silicon bring-up and yield improvement.\nSolid understanding of DFT techniques.\nProven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.\nExperience in MBIST architecture and insertion.\nExperience in analyzing and debugging simulation failures.\nSolid understanding of digital logic fundamentals.\nStrong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.\nProficiency with Perl or other scripting languages.\nStrong communication and interpersonal skills.\nPlus: Experience in STA constraint development in DFT modes\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. 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