{"id":454961,"url":"https://alion.io/job/broadcom-iii-v-wafer-fab-process-engineer-lithography","title":"III-V Wafer Fab Process Engineer (Lithography)","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":88,"open_postings":68,"ghost_share":0,"stale_share":0.5,"repost_share":0,"time_to_fill_p50_days":35,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Semiconductors","role_family":"Semiconductors","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":88000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":40},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"CAPA","optional":false},{"name":"Design of Experiments","optional":false},{"name":"FMEA","optional":false},{"name":"Photolithography","optional":false},{"name":"Plasma Etch","optional":false},{"name":"Statistical Process Control","optional":false}],"status":"closed","first_seen_at":"2026-08-02T00:00:00Z","employer_posted_date":"2026-08-02","last_verified_at":"2026-10-28T03:32:07Z","board_verified":false,"closed_at":"2026-10-28T03:32:07Z","days_open":87,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":87},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nPosition Summary\nThe III-V Wafer Fab Process Engineer is responsible for developing, qualifying, and sustaining photolithography and etch processes used in the manufacture of III-V compound semiconductor devices, including InP and GaAs based technologies. The engineer will establish robust manufacturing processes for R&D, new product, optimize yield and process capability, support high-volume manufacturing, and collaborate with cross-functional teams to deliver reliable and cost-effective manufacturing solutions.\nKey Responsibilities\nDevelop and optimize photolithography processes for III-V wafer fabrication.\nEstablish process windows for critical lithography parameters, including:\nPhotoresist coating, bake and develop\nExposure dose and focus\nOverlay accuracy\nCritical dimension (CD) control\nPattern fidelity and defectivity\nQualify new photoresists, developers, bottom anti-reflective coatings (BARC), and lithography materials.\nDevelop processes for broadband, i-line, DUV (193 nm), aligner/stepper/scanner platforms.\nOptimize lift-off lithography processes for metal patterning.\nMinimize defects such as particles, bridging, resist lifting, and pattern collapse.\nMask Layout and reticle design / tape out\nProcess Qualification\nDevelop qualification plans for new lithography and etch equipment.\nDefine process acceptance criteria and process capability targets.\nConduct Design of Experiments (DOE) to optimize process windows.\nPerform process characterization and statistical analysis.\nManufacturing Support\nMonitor process health using SPC.\nInvestigate process excursions and implement corrective and preventive actions.\nTroubleshoot lithography and etch-related issues affecting yield or productivity.\nSupport engineering lots, pilot production, and high-volume manufacturing.\nYield Improvement\nAnalyze yield loss associated with lithography and etch processes.\nPerform root cause analysis using 8D, 5 Why, Fishbone, and FMEA methodologies.\nDrive continuous improvement projects to reduce defects and improve process capability.\nProcess Control & Documentation\nDevelop and maintain: WI, Control Plans, PFMEA, OCAP, Process Recipes, ECO\nQualifications\nBachelor's, Master's, or PhD in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or Microelectronics.\n10+ years of semiconductor wafer fabrication experience.\nMinimum 10 years of direct experience in lithography and/or plasma etch processes.\nExperience with III-V semiconductor manufacturing is highly preferred.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.","description_format":"text","description_chars":3315,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["RF & Wireless Hardware","Virtualization & Containers","Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-06T09:28:56Z"},{"event":"close","at":"2026-10-28T03:32:07Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/broadcom-iii-v-wafer-fab-process-engineer-lithography","json_url":"https://alion.io/job/broadcom-iii-v-wafer-fab-process-engineer-lithography.json","meta":{"generated_at":"2026-10-28T05:45:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7547,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":95},"rest":"https://alion.io/mcp/rest/get_company?id=95"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fbroadcom-iii-v-wafer-fab-process-engineer-lithography"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fbroadcom-iii-v-wafer-fab-process-engineer-lithography"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fbroadcom-iii-v-wafer-fab-process-engineer-lithography"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/broadcom-iii-v-wafer-fab-process-engineer-lithography\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fbroadcom-iii-v-wafer-fab-process-engineer-lithography"}]}