{"id":66708,"url":"https://alion.io/job/broadcom-lead-asic-design-engineer","title":"Lead ASIC Design Engineer","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":89,"open_postings":70,"ghost_share":0,"stale_share":0.457,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":143800,"max":230000,"currency":"USD","period":"year","gross":null,"usd_annual":230000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence JasperGold","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-06-19T00:00:00Z","employer_posted_date":"2026-06-19","last_verified_at":"2026-10-23T11:07:28Z","board_verified":false,"closed_at":null,"days_open":129,"trust":{"level":"stale","repost_count":1,"flags":["stale"],"days_open":128},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nWe are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you will be the primary technical anchor responsible for the top-level architecture, microarchitecture, and full chip integration. You will guide a cross-disciplinary team spanning analog design, physical design, and verification, owning the design outcome end-to-end from early product definition to a successful foundry tape-out.\nLeadership & Strategic Responsibilities\nTechnical Ownership: Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.\n\nCross-Discipline Alignment: Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.\n\nTape-Out Delivery: Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.\n\nMentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team.\n\nTechnical Execution Responsibilities\nRTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).\n\nTiming & Constraint Ownership: Drive top-level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block-level timing budgets for the PD team.\n\nFront-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).\n\nIP Management: Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP.\n\nSilicon Validation: Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases.\n\nRequired Qualifications\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\nExperience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.\n\nRTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.\n\nTool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).\n\nSilicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.\n\nCommunication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project.\n\nWork Authorization: Must have legal authorization to work in the US.\n\nPreferred & Bonus Skills\nExperience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects).\n\nFamiliarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan.\n\nProficiency in scripting (Python, Tcl, Perl) to automate and streamline front-end design flows.\n\nAdditional Job Description:\nCompensation and Benefits\nThe annual base salary range for this position is $143,800 - $230,000.\nAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.","description_format":"text","description_chars":4944,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["RF & Wireless Hardware","Virtualization & Containers","Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-06-19T00:00:00Z"},{"event":"close","at":"2026-08-20T17:15:40Z"},{"event":"reopen","at":"2026-09-01T19:24:13Z"}],"visa":[],"liveness":{"score":14,"band":"cold","label":"Long shot","p_open":1,"p_active":0.483,"p_room":0.28,"age_days":128,"expected_fill_days":34,"reasons":["conf:42","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":{"stated_usd_annual":230000,"is_top_pay":true},"html_url":"https://alion.io/job/broadcom-lead-asic-design-engineer","json_url":"https://alion.io/job/broadcom-lead-asic-design-engineer.json","meta":{"generated_at":"2026-10-26T00:10:05Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":130,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":95},"rest":"https://alion.io/mcp/rest/get_company?id=95"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fbroadcom-lead-asic-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fbroadcom-lead-asic-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fbroadcom-lead-asic-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/broadcom-lead-asic-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fbroadcom-lead-asic-design-engineer"}]}