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Salary
$122k – $195k per year
Location
In office (Fort Collins, San Jose)
Seniority
Staff · 8+ years exp
Employment
Full-Time
Overview
Company
Impact
Profile match
Broadcom is an American semiconductor and infrastructure software company headquartered in Palo Alto, California, whose chip lineage runs back through Avago to the Hewlett-Packard components division. It designs networking switch and routing silicon that carries a large share of data centre traffic, custom AI accelerators built for hyperscale customers, plus wireless, broadband, storage and optical components. A sequence of very large acquisitions, culminating in the sixty-nine billion dollar purchase of VMware in 2023, has made infrastructure software roughly as important as chips to the group, and it is one of the most valuable listed technology companies in the world.

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Job Description:

We are seeking a Digital Mixed-Signal Lead with a strong digital design and architecture background to lead the development of digital control infrastructures for advanced clocking sub-systems (PLLs, FLLs, and DLLs).

Core Responsibilities

  • Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.

  • Logic Design: Design complex digital control loops, state machines for adaptive calibration, DVFS (dynamic voltage/frequency scaling) controllers, and fractional-N delta-sigma modulators.

  • Analog Interface: Serve as the primary bridge to Analog Circuit Designers. Translate analog specifications into robust digital architectures and define clean boundaries at the analog-digital interface.

  • Verification Partnership: Partner with Verification Teams to drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations.

  • Physical Design Collaboration: Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.

  • Sign-off Methodology: Enforce a rigorous full-chip CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) sign-off methodology for the clocking network.

Candidate Requirements

  • Education: Bachelors degree

  • Experience: 8+ years of professional digital ASIC design experience.

  • RTL Mastery: Deep expertise in writing robust, synthesizable SystemVerilog RTL

  • Process Nodes: Direct experience with advanced technology nodes, specificallyN5, N3P, and beyond.

  • Track Record: Proven history of steering cross-functional execution from initial concept through to successful tapeouts.

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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