{"id":2128915,"url":"https://alion.io/job/broadcom-principal-die-to-die-interconnect-modeling-architect","title":"Principal Die-to-Die Interconnect Modeling Architect","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":66,"ghost_share":0.015,"stale_share":0.545,"repost_share":0.015,"time_to_fill_p50_days":35,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States","Fort Collins, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":167500,"max":268000,"currency":"USD","period":"year","gross":null,"usd_annual":268000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-08T00:00:00Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-11-01T16:25:39Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nWe are seeking a Modeling Architect to lead a technical team in building and evolving our foundational modeling platform for die-to-die (D2D) PHYs designs. This role focuses on communication theory, algorithm development, system-level modeling, performance prediction, adaptation algorithm modeling, and architectural verification\nThe successful candidate will perform evaluation and tradeoff analysis using statistical tools over different signaling schemes (e.g., NZR vs. other), and analyze hardware architecture and implementation tradeoffs (equalization, error terms, noise budgets, etc.). Leading a technical team, the architect will drive algorithm verification of Verilog implementations, predictive adaptation algorithm run-time modeling, Monte Carlo evaluations of adaptation algorithms, and architectural verification with silicon correlation to achieve high model-to-silicon alignment.\nThis role requires deep technical understanding of communication algorithms, timing and margin budgeting, equalization and error term analysis, and focus on cross-functional technical leadership.\nKey Responsibilities\nSystem Modeling and Performance Prediction\nDevelop comprehensive behavioral and architectural models that accurately predict complete link behavior before implementation.\nBuild system-level models using MATLAB, Python, SystemC, or equivalent modeling environments.\nModel transmitter, receiver, package, channel, clocking, equalization, adaptation, and protocol interactions.\nPredict link performance including BER, latency, throughput, bandwidth density, power consumption, energy efficiency, and manufacturing margin.\nPerform architectural sensitivity analyses across process, voltage, temperature (PVT), aging, package variation, jitter, noise, and channel impairments.\nApply communication theory to help develop robust, high-performance signaling architectures.\nAnalyze equalization, timing recovery, clock recovery, calibration, and adaptive signal processing algorithms.\nEvaluate convergence behavior, numerical stability, hardware efficiency, and implementation feasibility.\nGuide algorithm development from mathematical concepts through production silicon implementation.\nModel deterministic and random timing uncertainties including jitter, skew, supply noise, process variation, and environmental effects.\nEstablish margin methodologies that ensure robust operation across manufacturing and operating conditions.\nCollaborate with implementation teams to ensure timing assumptions are achievable in silicon.\nArchitectural Verification and Silicon Correlation\nDefine the architectural verification strategy to ensure system requirements are traceable from concept through production silicon.\nDevelop behavioral reference models that serve as the golden standard for RTL implementation, verification, software development, and silicon validation.\nEstablish architecture-level performance metrics, verification methodologies, and success criteria.\nDrive correlation between behavioral models, RTL simulation, laboratory characterization, and production silicon.\nValidate architectural assumptions through simulation and silicon measurements, identifying performance gaps and driving corrective actions.\nDevelop verification methodologies that account for implementation effects including finite precision, analog non-idealities, and hardware constraints.\nDefine comprehensive validation strategies covering nominal operation, corner cases, interoperability, and robustness across all operating conditions.\nTechnical Leadership\nProvide technical leadership across architecture, analog, digital, firmware, packaging, signal integrity, verification, validation, and product engineering organizations.\nLead architecture reviews and critical technical decision-making throughout the product lifecycle.\nMentor engineers and architects in communication systems, modeling, and architecture development.\nInfluence technology roadmaps and drive innovation in next-generation die-to-die communication systems.\nRequired Qualifications\nMS in Electrical Engineering, Computer Engineering, and 15 or more years in related field experience; or PhD in Electrical Engineering, Computer Engineering, and 12 or more years in related field experience.\nDeep understanding of communication theory, equalization, and adaptive algorithms.\nExperience in high-speed SerDes, or D2D communication systems architecture.\nExtensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools.\nExperience with architecture model to RTL to verification\nExperience leading architectural verification, silicon correlation, and performance validation across multidisciplinary engineering teams.\nDesired Qualifications\nDemonstrated expertise in D2D, UCIe, or other short-reach die-to-die communication.\nExpertise in advanced packaging including silicon interposers, EMIB, hybrid bonding, and 3D integration.\nManagement experience\nCompensation and Benefits\nThe annual base salary range for this position is USD 167,500.00 To USD 268,000.00\nAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.","description_format":"text","description_chars":6565,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["RF & Wireless Hardware","Virtualization & Containers","Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-09T00:50:07Z"}],"visa":[],"liveness":{"score":54,"band":"ok","label":"Likely open","p_open":1,"p_active":0.599,"p_room":0.9,"age_days":24,"expected_fill_days":35,"reasons":["conf:0","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-11-01T06:10:25Z"},"pay":{"stated_usd_annual":268000,"is_top_pay":true},"html_url":"https://alion.io/job/broadcom-principal-die-to-die-interconnect-modeling-architect","json_url":"https://alion.io/job/broadcom-principal-die-to-die-interconnect-modeling-architect.json","meta":{"generated_at":"2026-11-01T21:06:28Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":32287,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":95},"rest":"https://alion.io/mcp/rest/get_company?id=95"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fbroadcom-principal-die-to-die-interconnect-modeling-architect"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fbroadcom-principal-die-to-die-interconnect-modeling-architect"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fbroadcom-principal-die-to-die-interconnect-modeling-architect"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/broadcom-principal-die-to-die-interconnect-modeling-architect\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fbroadcom-principal-die-to-die-interconnect-modeling-architect"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2128915}},{"tool":"search_jobs","arguments":{"company":"broadcom.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2128915},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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