{"id":39131,"url":"https://alion.io/job/broadcom-rd-engineer-ic-design-4","title":"R&D Engineer IC Design 4","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":92,"ghost_share":0.011,"stale_share":0.576,"repost_share":0.011,"time_to_fill_p50_days":32,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":121900,"max":195000,"currency":"USD","period":"year","gross":null,"usd_annual":195000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys Formality","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-07-28T00:00:00Z","employer_posted_date":"2026-07-28","last_verified_at":"2026-10-16T03:30:29Z","board_verified":true,"closed_at":null,"days_open":80,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":80},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nYou will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.\n·Ability to work independently as well as part of a large team spanning multiple geographies.\n·Education: BS/MS in Electrical or Computer Engineering or equivalent\n·Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience\n·Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.\n·Requires proficiency with the following design tools / flows:\n·TCL/Perl scripting\n·Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler\n·Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries\n·Understanding of liberty LIB models for timing\n·Formal verification (Synopsys Formality / Cadence Conformal)\n·Spyglass Lint\n·Power analysis of RTL and gate level netlists\n·Familiarity with DFT (design for test) and scan methodology\n·Version control (svn, git, etc)\nCompensation and Benefits\nThe annual base salary range for this position is USD 121,900.00 To USD 195,000.00\nAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.","description_format":"text","description_chars":3076,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["RF & Wireless Hardware","Virtualization & Containers","Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-07-28T00:00:00Z"},{"event":"close","at":"2026-08-24T00:14:02Z"},{"event":"reopen","at":"2026-09-01T19:09:13Z"}],"visa":[],"liveness":{"score":10,"band":"cold","label":"Long shot","p_open":1,"p_active":0.36,"p_room":0.28,"age_days":80,"expected_fill_days":32,"reasons":["conf:2","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-16T05:45:00Z"},"pay":{"stated_usd_annual":195000,"is_top_pay":true},"html_url":"https://alion.io/job/broadcom-rd-engineer-ic-design-4","json_url":"https://alion.io/job/broadcom-rd-engineer-ic-design-4.json","meta":{"generated_at":"2026-10-16T18:08:07Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3039,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-17T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":95},"rest":"https://alion.io/mcp/rest/get_company?id=95"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fbroadcom-rd-engineer-ic-design-4"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fbroadcom-rd-engineer-ic-design-4"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fbroadcom-rd-engineer-ic-design-4"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/broadcom-rd-engineer-ic-design-4\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fbroadcom-rd-engineer-ic-design-4"}]}