{"id":4220456,"url":"https://alion.io/job/broadcom-rd-engineer-physical-design-2","title":"R&D Engineer Physical Design","company":{"id":95,"name":"Broadcom","domain":"broadcom.com","url":"https://alion.io/company/broadcom","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":63,"ghost_share":0.032,"stale_share":0.556,"repost_share":0.032,"time_to_fill_p50_days":37,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":143800,"max":230000,"currency":"USD","period":"year","gross":null,"usd_annual":230000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[],"status":"live","first_seen_at":"2026-11-12T00:00:00Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-13T04:35:33Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description:\nWe are looking for an experienced STA & Timing Closure Engineer to lead static timing analysis and signoff execution for high-complexity, multi-GHz System-on-Chip (SoC) architectures on advanced FinFET and GAA nodes (5nm, 3nm, 2nm). In this role, you will take end-to-end ownership of full-chip and block-level timing closure across complex multi-voltage, multi-frequency domains, ensuring first-pass silicon success while maximizing Performance, Power, and Area (PPA) metrics.\nKey Responsibilities Multi-Mode Multi-Corner (MMMC) STA: Architect, configure, and maintain rigorous STA environments across hundreds of process, voltage, temperature (PVT), and operational modes \nDevelop, audit, constraints for complex clock structures\nTiming Closure Loop Execution: Collaborate closely with physical design teams to analyze timing bottlenecks; generate precise ECOs-both automated and functional/manual.\nFoundry Interface & Signoff Verification: Validate timing margins against foundry standard cell, macro, and interface IP characterization data. Run strict signoff audits to guarantee zero critical timing violations prior to tapeout.\nRequirements:\nBS Degree in Electrical Engineering and 12+ years related experience or MS in Electrical Engineering and 10+ years related work experience.\nCompensation and Benefits\nThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00\nAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. 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