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Salary
$85k – $120k per year
Location
In office (Upton)
Seniority
Middle · 3+ years exp
Visa
H-1B filings in 12 months: 368
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 19, 2026. First seen by Alion on Oct 5, 2026. Brookhaven National Laboratory scores A on the Alion truth index.

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Brookhaven National Laboratory is a multidisciplinary government research institution located in Upton, New York (Long Island). Founded in 1947 at the former site of Camp Upton, the laboratory operates under the oversight of the U.S. Department of Energy (DOE) Office of Science and is managed by Brookhaven Science Associates (BSA) - a partnership between Stony Brook University and Battelle Memorial Institute.

The mission of the Instrumentation Division is to develop state-of-the-art instrumentation required for experimental research programs at Brookhaven Lab and to maintain the expertise and facilities in specialized high technology areas essential for this work. Development of facilities is motivated by present Brookhaven research programs and anticipated future directions of research. Our work has a significant impact on programs throughout the world that rely on state-of-the-art radiation detectors, readout electronics, data acquisition systems, and scientific instrumentation.

We seek a motivated Digital ASIC Design Engineer to join our team as a digital designer for developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.

In this role, you will to the architecture, RTL design, implementation, and integration of digital blocks and subsystems for mixed-signal ASICs used in detector readout, trigger and timing distribution, data concentration, control, calibration, and high-speed data transmission. You will collaborate closely with analog and mixed-signal designers, verification engineers, physical design engineers, firmware developers, detector scientists, and other technical team members in the ASIC group, the Instrumentation Division, and the broader scientific community. We look for candidates with strong digital ASIC design expertise, particularly in low-power, radiation-aware, timing-critical, and data-intensive systems for scientific applications.

Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high-resolution X- and gamma-ray spectrometers, high-rate photon counters and imagers, cryogenic and radiation-tolerant instrumentation, and other specialized systems for high-energy physics, nuclear physics, photon sciences, quantum information science, and related scientific programs. Our ASICs may operate in extreme environments, must meet stringent power, timing, noise, and radiation requirements, and must integrate reliably with sensors, FPGAs, data acquisition systems, and laboratory test infrastructure. The applications of these ASICs extend beyond BNL to national and international user facilities: your work will have the potential to shape the instruments used for scientific discovery and engineering advancements across the globe!

Essential Duties and Responsibilities:

  • Take a proactive role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs
  • Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders
  • Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces
  • Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration
  • Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments
  • Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration
  • Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout
  • Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems
  • Create technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies
  • Demonstrated commitment to working safely, acting ethically, and taking personal accountability for operational excellence

Required Knowledge, Skills, and Abilities:

  • Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study
  • Some experience with developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs
  • Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation
  • Familiarity with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems
  • Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges
  • Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams

Preferred Knowledge, Skills, and Abilities:

  • Minimum three (3) years progressively responsible related work experience in digital ASIC design
  • Experience in a research environment (particularly in academic, or national laboratory or semiconductor industry) highly preferred
  • Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study
  • Experience with readout integrated circuits for radiation detectors, including detector timing, triggering, sparsified data readout, high-speed data transmission, calibration, and slow-control functions
  • Experience with ASICs for particle physics, nuclear physics, photon sciences, cryogenic instrumentation, space or radiation environments, or other scientific applications
  • Experience with digital implementation tools and flows such as synthesis, static timing analysis, formal equivalence checking, lint, CDC/RDC analysis, power analysis, DFT/scan, and automated place and route
  • Familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols
  • Experience with scripting and automation using Tcl, Python, Perl, Make, shell scripting, or similar tools in an EDA environment
  • Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation
  • Experience working with firmware, FPGA prototyping, board-level test systems, and laboratory characterization of ASICs

Additional Information:

  • This is a fully onsite position located at Brookhaven National Laboratory in Upton, NY.

Brookhaven National Laboratory is committed to providing fair, equitable and competitive compensation. This is a multi-level role and the full salary range for this position is $85000 - $120000 / year. You will be placed at the level and salary commensurate with your experience. Salary offers will be commensurate with the final candidate’s qualification, education and experience and considered with the internal peer group.

Brookhaven National Laboratory is committed to employee success and we believe that a comprehensive employee benefits program is an important and meaningful part of the compensation employees receive. Review more information atBNL | Benefits Program

Brookhaven National Laboratory requires all non-badged personnel including visitors to produce a REAL-ID or REAL-ID compliant documentation to access Brookhaven National Laboratory - view more information at www.bnl.gov/real-id. This is due to nationwide identification requirements for federal site access as required by the federal REAL ID Act. Those not in possession of a REAL ID-compliant document will not be permitted to access the site which includes access to the Laboratory for interviews.

As a U.S. Department of Energy laboratory, Brookhaven National Laboratory requires employees to obtain and maintain a DOE Uncleared Personal Identity Verification (UPIV) credential in accordance with Homeland Security Presidential Directive 12 (HSPD-12) requirements. The credentialing process is completed as part of onboarding and enables access to DOE facilities and information systems. As a condition of employment, the selected candidate must be able to obtain and maintain a UPIV credential. These requirements are established under DOE Order 206.2 Chg. 2, Identity, Credential, and Access Management (ICAM- Identity, Credential, and Access Management (ICAM)), and DOE Order 473.1A- Physical Protection Program- Physical Protection Program.

About Us

Brookhaven National Laboratory (www.bnl.gov) delivers discovery science and transformative technology to power and secure the nation’s future. Brookhaven Lab is a multidisciplinary laboratory with seven Nobel Prize-winning discoveries, 37 R&D 100 Awards, and more than 70 years of pioneering research. The Lab is primarily supported by the U.S. Department of Energy’s (DOE) Office of Science. Brookhaven Science Associates (BSA) operates and manages the Laboratory for DOE. BSA is a partnership between Battelle and The Research Foundation for the State University of New York on behalf of Stony Brook University. BSA salutes our veterans and active military members with careers that leverage the skills and unique experience they gained while serving our country, learn more at BNL | Opportunities for Veterans at Brookhaven National Laboratory.

Equal Opportunity/Affirmative Action Employer

Guided by our core values of integrity, responsibility, innovation, respect, and teamwork, Brookhaven Science Associates is an Equal Employment Opportunity Employer-Vets/Disabled. We are committed to fostering a respectful and collaborative environment that fuels scientific discovery. We consider all qualified applicants without regard to any characteristic protected by law. All qualified individuals are encouraged to apply. We ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. *VEVRAA Federal Contractor

BSA employees are subject to restrictions related to participation in Foreign Government Talent Recruitment Programs, as defined and detailed in United States Department of Energy Order 486.1A. You will be asked to disclose any such participation at the time of hire for review by Brookhaven. The full text of the Order may be found at: https://www.directives.doe.gov/directives-documents/400-series/0486.1-BOrder-a/@@images/file

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