{"id":107588,"url":"https://alion.io/job/cadence-design-engineering-architect","title":"Design Engineering Architect","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":109,"ghost_share":0,"stale_share":0.78,"repost_share":0,"time_to_fill_p50_days":58,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":31000,"max_usd":65000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-06-04T00:00:00Z","employer_posted_date":"2026-06-04","last_verified_at":"2026-11-13T22:54:37Z","board_verified":true,"closed_at":null,"days_open":162,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":162},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.\nJob Responsibilities:\nDesign of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)\nDesign and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications\nWork closely with Layout Design Engineers to design IC circuit blocks and PMA sections\nWork with Technical Team Leads in the areas of circuit design and SERDES architectures\nWork with global teams (US, west coast and east coast), which work in different time-zones\nJob Qualifications:\nBEng, MEng, PhD or equivalent.\nCandidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design\nShould have a good understanding of jitter and signal equalization techniques\nDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators\nExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment\nPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verification\nAdditional Skills/Preferences:\nCadence tool experience is desirable and design experience at >10Gbps and in Lab test experience as part of silicon evaluation is advantageous\nWe’re doing work that matters. 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