{"id":2413133,"url":"https://alion.io/job/cadence-design-systems-design-engineer-i","title":"Design Engineer I","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":101,"ghost_share":0,"stale_share":0.812,"repost_share":0,"time_to_fill_p50_days":47,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cary, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":88900,"max":165100,"currency":"USD","period":"year","gross":null,"usd_annual":165100},"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-12T00:00:00Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-14T18:33:13Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nWe are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform…\nAs such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.\nA bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments.\nKey responsibilities:\nDefine and implement SoC level DFT architecture for large and complex designs.\nDevelop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.\nPerform DFT insertion, verification, and coverage analysis at block and SoC levels.\nDrive pre-silicon DFT sign-off, including DRC closure and coverage targets.\nSupport post-silicon debug, failure analysis and yield learning.\nCollaborate with RTL, verification, physical design and operation teams.\nQualifications:\nBS degree\nAt least 3 years of hands-on experience in SoC DFT.\nMust-have skills:\nStrong expertise in SCAN, ATPG, MBIST.\nExperience with pre-silicon validation and post-silicon debug.\nStrong problem solving and debugging skills.\nAbility to work effectively in a cross-functional engineering environment.\nGood-to-have skills:\nScripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.\nExperience with IP-level DFT integration and reuse.\nExposure to low-power DFT considerations and complex clocking architectures.\nFamiliarity with manufacturing test flows and silicon yield improvement.\nThe annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.\nWe’re doing work that matters. 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