{"id":2870692,"url":"https://alion.io/job/cadence-design-systems-design-engineer-ii-6","title":"Design Engineer II","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":111,"ghost_share":0,"stale_share":0.73,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-09-07T00:00:00Z","employer_posted_date":"2026-09-07","last_verified_at":"2026-10-30T00:10:28Z","board_verified":true,"closed_at":null,"days_open":53,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":53},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Opportunity: Foundry PDK Design Enablement Engineer\nExperience Level: 2-4 Years\nDepartment: Methodology & Flow Enablement Group\nEducation: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field\nPosition Overview\nWe are seeking a highly motivated Foundry Process Technology, PDK & DTCO Engineer with 2-4 years of experience to join our process technology group. In this role, you will bridge the gap between process technology and design, driving next-generation semiconductor technology through cutting-edge path-finding methodologies. The ideal candidate possesses a strong foundation in PDK enablement, physical verification decks, process/design interaction electrical studies, Spice model understanding and design automation.\nKey Responsibilities\nPDK Enablement: Validate, deploy, and maintain foundational PDK components specifically tailored for advanced technology nodes.\n Technology Study Activities: Conduct rigorous standard cell, SRAM, and custom circuit benchmarking alongside interconnect optimization to maximize power, performance, and area (PPA).\nAutomation & Methodology: Design, develop, and maintain robust scripts and automated execution flows for PDK enablement/validation and PDK analysis.\nCollaborative Path-Finding: Partner closely with internal DTCO groups to turn advanced device architectures into reality.\nRequired Qualifications & Technical Skills\nIndustry Experience: 2-4 years of hands-on experience in semiconductor technology analysis, foundry PDK enablement, and the co-optimization of PDK components like LVS, DRC, Parasitic Extraction, spice models. Strong understanding of PDK design enablement flows. Exposure to multiple foundry & nodes is a plus.\n Device Physics: Strong fundamental understanding of CMOS device physics, including advanced architectures like GAA (Gate-All-Around), FinFETs, and planar MOSFETs.\n Physical Verification & EDA: Deep knowledge of Layout Versus Schematic (LVS), Design Rule Checking (DRC), Parasitic Extractions, and Spice models at transistor level. Cadence based tool knowledge is a plus.\nTooling Familiarity: Direct experience or high proficiency with Cadence-based tool suites is highly advantageous.\nTeam Collaboration: Proven experience interfacing with core PDK development teams, technology enablement units, or advanced technology benchmarking groups.\nWe’re doing work that matters. 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