{"id":3788897,"url":"https://alion.io/job/cadence-design-systems-design-engineering-architect-systems-and-interfaces","title":"Design Engineering Architect – Systems and Interfaces","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":109,"ghost_share":0,"stale_share":0.761,"repost_share":0,"time_to_fill_p50_days":60,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States","Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":185500,"max":344500,"currency":"USD","period":"year","gross":null,"usd_annual":344500},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Edge AI","optional":false},{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-04T00:00:00Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-10T23:46:00Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nDesign Engineering Architect - Systems and Interfaces\nSan Jose\nJob Description:\nThe SSG Central Applications Engineering team seeks an experienced SoC design engineer to enable the integration and deployment of Cadence IP in complex customer system designs. As a Design Engineering Architect, you will serve as a senior technical leader, enablingthe successful integration and adoption of Cadence interface IP in our customers’ SoCs.\nIn this role, you will work closely with the SSG IP sales, marketing, development engineering, and customer support teams. You will contribute to product definition, develop technical content and examples, and drive complex pre-sales and post-sales engagements.\nThe Cadence Silicon Solutions Group (SSG) develops and licenses IP for SoC and ASIC designs, including high-performance DSPs, CPUs, interface IP, DDR controllers, hardware accelerators, and subsystems. These technologies enable applications such as machine learning, edge AI, radar, audio, speech, and vision. Leading semiconductor companies use Cadence IP in billions of chips shipped annually. This role enables customer adoption of Cadence IP and addresses complex system integration challenges.\nResponsibilities:\nServe as the technical authority for Cadence interface controllers and system-level IP integration in customer engagements.\nLead resolution of critical customer issues and escalations, coordinating with development engineering, sales, marketing, and customer support teams on pre-sales and post-sales engagements.\nDevelop reference designs, technical collateral, and application notes for IP integration, SoC design, and verification. \nDevelop and deliver training for customers and field application engineers.\nProvide advanced technical guidance to customers, support teams, and field application engineers on IP integration, configuration, and system-level deployment.\nLead product evaluations and release-readiness reviews, identifying integration risks, usability gaps, and advanced customer use cases. \nAnalyze and propose enhancements to our products and documentation based on customer needs and use cases.\nRequired Skills:\nDemonstrated expertise in the RTL design, verification, and debug of high-speed interface protocols such as PCIe, UCIe, and Ethernet.\nExperience integrating IP into complex SoCs, with a strong understanding of system architecture, interfaces, and on-chip interconnects.\nExperience with AMBA protocols, including ACE, CHI, AXI, and APB.• Proficient in writing and debugging RTL (Verilog, SystemVerilog).\nExperience with end-to-end SoC implementation flows, including RTL synthesis, design constraints, DFT, CDC, and static timing analysis.\nDemonstrated ability to analyze complex hardware and system problems, identify root causes, and drive cross-functional teams to resolution.\nStrong written and verbal communication skills. \nA BS in EE/CS with 12+ years, or an MS in EE/CS with 8+ years of relevant work experience.\nAbility to travel up to 10% of the time, including internationally.\nThe annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":3815,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-05T05:18:19Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 368 · green card filings: 176","filings_12m":368,"filings_prev_12m":268,"green_card_filings_12m":176,"median_offered_wage_usd":150882,"route":null,"cap_exempt":false,"checked_at":"2026-11-10T11:34:35+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":117}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":6,"expected_fill_days":60,"reasons":["conf:4","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-11-10T06:52:35Z"},"pay":{"stated_usd_annual":344500,"is_top_pay":true},"html_url":"https://alion.io/job/cadence-design-systems-design-engineering-architect-systems-and-interfaces","json_url":"https://alion.io/job/cadence-design-systems-design-engineering-architect-systems-and-interfaces.json","meta":{"generated_at":"2026-11-11T04:20:28Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4685,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-design-engineering-architect-systems-and-interfaces"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-design-engineering-architect-systems-and-interfaces"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-design-engineering-architect-systems-and-interfaces"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-design-engineering-architect-systems-and-interfaces\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-design-engineering-architect-systems-and-interfaces"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3788897}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3788897},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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