{"id":4146709,"url":"https://alion.io/job/cadence-design-systems-design-verification-architect","title":"Design Verification Architect","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":108,"ghost_share":0,"stale_share":0.787,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-11-14T05:58:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-11-11T00:00:00Z","employer_posted_date":"2026-11-11","last_verified_at":"2026-11-14T05:09:42Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Formal Verification Architect, PCIe & UALink Controllers\nRole Summary\nWe are looking for an experienced Formal Verification Architect to lead the formal verification strategy for high-performance PCIe and UALink controller IP.\nThe ideal candidate will combine deep formal verification expertise with strong protocol and microarchitecture knowledge. This is a hands-on technical leadership role responsible for defining verification architecture, identifying high-value formal targets, solving complex proof problems, and driving formal methods throughout the IP development lifecycle.\nKey Responsibilities\nDefine the formal verification architecture and methodology for PCIe and UALink controller IP.\nDevelop block, subsystem, and end-to-end formal verification strategies spanning:Protocol engines and state machines\nTransaction and packet processing\nFlow control and credit management\nOrdering and dependency rules\nReplay, retry, recovery, and error handling\nArbitration, scheduling, and resource management\nPower/reset and initialization sequences\nConfiguration and control logic\n\nIdentify areas where formal verification can provide stronger coverage than simulation, especially for corner cases, deadlocks, livelocks, starvation, ordering violations, data integrity, and protocol compliance.\nArchitect assume-guarantee, compositional, abstraction, and formal decomposition strategies for large and complex controller designs.\nDevelop reusable SystemVerilog Assertions (SVA), properties, checkers, constraints, and formal verification IP.\nDrive convergence of difficult proofs through abstraction, cut-points, state-space reduction, invariants, partitioning, and proof-debug techniques.\nWork closely with RTL architects and designers to improve design-for-formal-verification and resolve architectural ambiguities early.\nDefine formal coverage criteria and establish metrics for proof completeness, unreachable states, vacuity, assumptions, and coverage closure.\nLead formal analysis of complex bug classes that are difficult to expose through constrained-random simulation.\nEstablish the appropriate balance between formal, simulation, emulation, and system-level verification.\nReview verification plans and architecture specifications to identify formal opportunities and verification gaps.\nMentor verification engineers and raise formal verification capability across the broader controller verification organization.\nRequired Qualifications\nBS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.\nTypically 15+ years of Verification experience, with significant hands-on formal verification experience of 5 years at least.\nDeep expertise in property-based formal verification of complex RTL.\nDeep knowledge of PCI Express, preferably PCIe 5.0/6.0/7.0 controller architecture and verification.\nExperience with UALink, CXL, UCIe, Ethernet, or comparable high-performance interconnect protocols\nStrong knowledge of:SystemVerilog and SVA\nFormal property development\nAssumption and constraint modeling\nAbstraction and decomposition\nFormal coverage and proof closure\nCounterexample analysis and debug\n\nHands-on experience with industry formal platforms such as Cadence Jasper or Equivalent\nExperience applying formal verification to high-speed interconnect or networking controller designs.\nWe’re doing work that matters. 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