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This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.\nThis is a leadership role where you will be responsible for:\nTechnical Leadership:\nGuide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.\nDesign & Microarchitecture:\nDefine and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.\nRTL Development:\nWrite, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.\nVerification & Signoff:\nOversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.\nCollaboration:\nWork closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.\nQualifications:\n*10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences\n*Proven experience in leading and managing complex engineering projects\n*Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration\n*Expert in RTL design (Verilog), simulators debuggers\n*Hands on Experience in Synthesis, SDC creation and support PD and STA teams.\n*Experience in driving results in multi-disciplinary organization\nDesirable:\nA Self-motivated person with good communication and design management skills\nExperience with Cadence front end toolset\nWe’re doing work that matters. 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