{"id":2759756,"url":"https://alion.io/job/cadence-design-systems-intern-afg-memoire","title":"Intern AFG Memoire","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":110,"ghost_share":0,"stale_share":0.755,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Early Careers","role_family":"Early Careers","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Valbonne, France"],"countries":["FR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":24000,"max_usd":48000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":768},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-16T00:00:00Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-10-25T13:14:13Z","board_verified":true,"closed_at":null,"days_open":9,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":9},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.\nCadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace,industrial and health.\nWe are looking for a final-year engineering or Master’s student, or pursuing an equivalent qualification, in microelectronics, electronics, computer engineering, computer science, applied physics, data science, or a related discipline\nTitle: Intern\nLocation: Sophia-Antipolis, France\nDuration: 6 months\nFrom: early Q1 2027\nWe are considering three possible internship topics and expect to select for only one of them. When applying, please indicate the topic that best matches your interests and experience. You may also mention if you would be interested in extended topic.\nInternship 1: Advanced SRAM Design and Self-Timing Optimization\nInternship 2: Statistical Yield Optimization for Next-Generation SRAM Memories\nInternship 3: Power Characterization Methodology for Memory Compilers\nWhat Matters Most\nCuriosity, enthusiasm, and a desire to learn. Whether your background is in software, electronics, data science, AI, or another engineering field, we encourage you to apply.\nThis is an opportunity to gain hands-on experience in SRAM development and contribute to real-world projects spanning memory design, characterization, validation, and compiler implementation.\nInternship 1 : Advanced SRAM Design and Self-Timing Optimization\nInvestigate and optimize SRAM self-timing architectures to improve frequency and robustness for advanced technology nodes, through enhanced bitcell tracking methodologies and adaptive timing path design.\nAbout the Internship\nAdvanced embedded SRAMs must maintain both robustness and performance across increasingly challenging manufacturing process variations. One key aspect is the design of self-timing mechanisms that accurately track the behavior of memory bitcells under extreme process conditions.\nCurrent solutions combine bitcell tracking and logic-based timing paths, but opportunities exist to improve correlation with worst-case memory behavior while minimizing performance penalties.\nWhat You Will Do ·\nAnalyze the impact of advanced process variations on SRAM self-timing paths.\nStudy and benchmark different timing tracking methodologies.\nInvestigate bitcell-based and hybrid tracking architectures.\nDevelop simulation and evaluation methodologies. \nPropose and validate architectural improvements to improve performance while preserving robustness. \nRelevant knowledge and interests\nWe are interested in your foundational knowledge, curiosity, problem-solving approach and willingness to learn. You don’t need experience in every area listed below.\nMicroelectronics, CMOS circuit design, and SRAM architecture\nVLSI design, advanced technologies\nCircuit simulation and variability analysis \nMethodical mindset and good presentation skills \nExpected outcomes\nThe internship will provide hands-on exposure to industrial memory IP development and advanced-node design challenges, with the opportunity to contribute to methodologies used in next-generation embedded memory products.\nWe believe this topic would be an excellent opportunity for a curious student seeking experience in advanced integrated circuit design within a leading EDA and IP company. \nInternship 2 : Statistical Yield Optimization for Next-Generation SRAM Memories\nDevelop novel variation-aware methodologies to optimize SRAM robustness and yield under statistical process variations, while minimizing the impact on Performance, Power, and Area (PPA).\nAbout the Internship\nSRAM memories are a critical component of modern AI and high-performance computing systems. As technology scaling increases device variability, achieving extremely high yield targets requires advanced statistical design methodologies that go beyond conventional margin-based approaches. Optimally balancing robustness across bitcells, sense amplifiers, and peripheral circuits has become a major challenge for next-generation SRAM products.\nWhat You Will Do\nAnalyze the impact of statistical process variations on SRAM yield and robustness.\nInvestigate yield allocation strategies across SRAM building blocks.\nDevelop variation-aware design and optimization methodologies.\nEvaluate yield versus PPA trade-offs using advanced statistical analysis techniques.\nPropose and validate methodologies to improve overall SRAM robustness. \nRelevant knowledge and interests\nWe are interested in your foundational knowledge, curiosity, problem-solving approach and willingness to learn. You don’t need experience in every area listed below.\nMicroelectronics, CMOS circuit design and SRAM architecture\nCircuit simulation and interest in statistical analysis\nEDA methodology and tools enhancement\nLogical reasoning and methodical approach to problem solving \nExpected Outcomes\nThe internship will provide hands-on exposure to advanced SRAM design methodologies, high-sigma statistical analysis, and yield optimization techniques used in state-of-the-art memory IP development. The student will contribute to innovative robustness methodologies for future AI and high-performance computing products.\nInternship 3 : Power Characterization Methodology for Memory Compilers \nInvestigate and optimize power characterization methodologies for SRAM memory compilers to improve the accuracy of power models while limiting characterization time and simulation cost.You will explore stimuli definition, circuit simulation, characterization and interpolation strategies, and validation of power trends across different memory architectures, instance sizes, and design features.\nAbout the Internship\nPower consumption is a key competitive factor for embedded memory products. Providing accurate power models is essential to enable reliable power estimation and optimization during System-on-Chip design.\nMemory compilers can generate a large number of instances covering different memory sizes, architectures, configurations, and design features. An optimized characterization and interpolation strategy is therefore required to minimize the number of electrical simulations while maintaining accurate and consistent power models across the entire compiler solution space.\nThe generated power information is delivered through Liberty models and must exhibit physically consistent trends based on instance dimensions, memory architecture, operating mode, and enabled features. \nWhat You Will Do\nUnderstand memory compiler architectures and the different memory power modes.\nReview power stimuli, critical signals, initialization sequences and simulation settings.\nOptimize instance selection and interpolation to reduce simulation effort.\nValidate Liberty power trends across instance sizes, configurations and features.\nApply the methodology to different compilers, such as single-port, dual-port and ROM. \nRelevant knowledge and interests\nWe are interested in your foundational knowledge, curiosity, problem-solving approach and willingness to learn. You don’t need experience in every area listed below.\nMicroelectronics, CMOS circuit design, and SRAM architecture\nCircuit simulation and power analysis\nData analysis and scripting, preferably Python, Tcl or Shell\nAnalytical skills and interest in EDA methodologies \nExpected Outcomes ·\nThe internship will provide hands-on exposure to industrial memory IP development, transistor-level power analysis, electrical characterization flows, and the modeling methodologies used to support power estimation during System-on-Chip design. \nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":8185,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"France","iso":"FR","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-17T02:28:45Z"}],"visa":[],"liveness":{"score":57,"band":"ok","label":"Likely open","p_open":0.9,"p_active":0.632,"p_room":1,"age_days":9,"expected_fill_days":57,"reasons":["conf:70","stale_co","velocity","win:early","comp:junior,brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-intern-afg-memoire","json_url":"https://alion.io/job/cadence-design-systems-intern-afg-memoire.json","meta":{"generated_at":"2026-10-25T16:56:44Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24400,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-intern-afg-memoire"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-intern-afg-memoire"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-intern-afg-memoire"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-intern-afg-memoire\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-intern-afg-memoire"}]}