{"id":370121,"url":"https://alion.io/job/cadence-design-systems-lead-application-engineer-6","title":"Lead Application Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":110,"ghost_share":0,"stale_share":0.745,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shenzhen, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":56000,"max_usd":126000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Linux","optional":true},{"name":"Unix","optional":true}],"status":"live","first_seen_at":"2019-06-05T00:00:00Z","employer_posted_date":"2019-06-05","last_verified_at":"2026-11-01T18:37:05Z","board_verified":true,"closed_at":null,"days_open":2707,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":2706},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPrincipal Application Engineer (Front-end Verification)\nPosition Description:\n1. Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.\n2. Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.\n3. Train, ramp-up and accompany customer project.\n4. Conduct basic and advanced trainings, presentations and demos as necessary.\n5. Providing technical expertise to address clients’ queries, which need expert involvement.\n6. Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.\nPosition Requirements:\nOver 2~8 years’ experience in the following areas:\n1. 2.Design experience in Verilog/VHDL for IP or SoC chip level.\n2. HW verification with knowledge of System Verilog/VHDL and HDL simulators\n3. FPGA prototyping project experience\n4. Experience with hardware emulator or accelerator is a big advantage\n5. Advanced Verification Methodology like UVM is a plus\n6. Knowledge of Unix and Linux is highly desired\n7. Strong verbal and written communication skills in English\n8. Strong teamwork skills with good human relationship\nWe’re doing work that matters. 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