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This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.\nFeature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.\nExecution and Technical Leadership\nDevelopment: Write complex test cases and sequences to achieve high functional coverage.\nDebug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.\nConstraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.\nFormal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.\nMetric Management\nCoverage Analysis: Monitor and analyze functional and code coverage metrics.\nGate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.\nSign-off: Define the \"definition of done\" and provide final technical approval for the verification phase.\nSoft Skills and Leadership\nMentorship: Guiding junior engineers on coding standards and debugging techniques.\nCross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.\nProject Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.\nRequired Qualifications\nB.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field\n4-7 years of hands-on DV experience in semiconductor/ASIC/SoC companies\nWe’re doing work that matters. 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