{"id":2870704,"url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-14","title":"Lead Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":110,"ghost_share":0,"stale_share":0.727,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":21000,"max_usd":54000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Quantus","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-06-18T00:00:00Z","employer_posted_date":"2026-06-18","last_verified_at":"2026-10-22T06:53:03Z","board_verified":true,"closed_at":null,"days_open":127,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":127},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Responsibilities:\nThe Candidate will have design responsibility, including floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power / EM-IR signoff, physical verification (DRC/LVS/Antenna), and DFM Closure.\nPhysical design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools\nPhysical design for PPA optimization of performance and power-oriented best-in-class interface IPs such as DDR, LPDDR, PCIE, UCIE, etc and test chips for advanced process nodes, such as 7nm/5nm/3nm/2nm\nAn opportunity to work on many varieties of challenging designs, i.e., low power, high-speed and area optimized designs.\nWork closely with RTL design team & Analog Team to ensure on-time, successful tapeouts. \nRequired skills -\nB.Tech/BE/ME/Mtech with 4-6 years hands-on experience in physical design and physical verification.\nExperienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.\nSolid knowledge on physical design, static timing analysis, Low Power Design, EM/IR /crosstalk analysis, formal verification, physical verification, DFM, DFT.\nSuccessful track records of taping out complex IP’s & SoC’s at 16/10/7/5/3 nm with different foundries.\nPower user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus will be an added advantage\nAutomation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl/python assisted with AI.\nShould have excellent communication, analytical and problem-solving skills, should be self-motivated and good team player\nWe’re doing work that matters. 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