{"id":3665261,"url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-23","title":"lead Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":109,"ghost_share":0,"stale_share":0.761,"repost_share":0,"time_to_fill_p50_days":60,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-03T05:49:08Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-10T12:42:09Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description: Lead Design Engineer - UCIe Verification\nLocation: Bangalore, India\nFunction: Design Verification\nRole: Lead Design Engineer - UCIe Controller Verification\nRole Overview\nWe are looking for a highly motivated and technically strong Lead Design Engineer - Verification to join our UCIe verification team in Bangalore.\nThe candidate will contribute to the verification of complex UCIe Controller IP, working on next-generation chiplet and die-to-die interconnect solutions. The role requires strong hands-on expertise in SystemVerilog/UVM, verification architecture, coverage-driven verification, protocol verification, and debug.\nThe engineer will work closely with design, architecture, validation, and other cross-functional teams to develop scalable verification environments, validate complex protocol scenarios, drive coverage closure, debug failures, and contribute toward high-quality IP releases.\nRequired Qualifications\nBE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.\n5+ years of relevant Design Verification experience, with strong hands-on ownership of IP or subsystem-level verification.\nStrong expertise in: SystemVerilogUVM Constrained-random verificationFunctional coverageCode coverageAssertions/SVARegression and failure debug\nExperience developing reusable UVM testbench components and verification infrastructure.\nStrong understanding of verification methodology, test planning, coverage closure, and sign-off.\nExperience with industry-standard simulators/debug environments such as Cadence Xcelium or equivalent.\nAbility to analyze complex specifications and translate requirements into effective verification scenarios.\nStrong debugging and problem-solving skills.\nWe’re doing work that matters. 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